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set initial_sprs, cleanup mfspr testprog
author
Tobias Platen
<tplaten@posteo.de>
Thu, 7 Jan 2021 17:25:48 +0000
(18:25 +0100)
committer
Tobias Platen
<tplaten@posteo.de>
Thu, 7 Jan 2021 17:25:48 +0000
(18:25 +0100)
src/soc/fu/mmu/test/test_pipe_caller.py
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diff --git
a/src/soc/fu/mmu/test/test_pipe_caller.py
b/src/soc/fu/mmu/test/test_pipe_caller.py
index 71aae0159eb0a608a00a9162b35a40fc2b9bb1ea..e45b306522286c74dffce13c8c8ee20f618b542e 100644
(file)
--- a/
src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/
src/soc/fu/mmu/test/test_pipe_caller.py
@@
-77,15
+77,14
@@
class MMUTestCase(TestAccumulatorBase):
def case_mfspr_after_invalid_load(self):
lst = [ # TODO -- set SPR on both sinulator and port interface
def case_mfspr_after_invalid_load(self):
lst = [ # TODO -- set SPR on both sinulator and port interface
- "mfspr 1, 18", # DSISR to reg 1
-- KeyError: 2 in simulator
- "mfspr 2, 19", # DAR to reg 2
-- with key = spr_dict[key].SPR
+ "mfspr 1, 18", # DSISR to reg 1
+ "mfspr 2, 19", # DAR to reg 2
# TODO -- verify returned sprvals
]
initial_regs = [0] * 32
# TODO -- verify returned sprvals
]
initial_regs = [0] * 32
- initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
- 'XER': 0xe00c0000}
+ initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs)
self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs)