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test fixedload
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 4 Apr 2020 16:36:26 +0000
(17:36 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 4 Apr 2020 16:36:26 +0000
(17:36 +0100)
libreriscv
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src/soc/decoder/power_pseudo.py
patch
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src/soc/decoder/pseudo/parser.py
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src/soc/decoder/pseudo/pywriter.py
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diff --git
a/libreriscv
b/libreriscv
index 36ca948926f4c13b6e121948606a4d1aed8394f6..6ad52e429bfcc8f815de14109833eb9288bc9c86 160000
(submodule)
--- a/
libreriscv
+++ b/
libreriscv
@@
-1
+1
@@
-Subproject commit
36ca948926f4c13b6e121948606a4d1aed8394f
6
+Subproject commit
6ad52e429bfcc8f815de14109833eb9288bc9c8
6
diff --git
a/src/soc/decoder/power_pseudo.py
b/src/soc/decoder/power_pseudo.py
index c837ce8635bc85498ea02b496e7a5cfdd5d0d690..9ed8295126fe49c83cdeb835f258ebf6191fb7d7 100644
(file)
--- a/
src/soc/decoder/power_pseudo.py
+++ b/
src/soc/decoder/power_pseudo.py
@@
-107,8
+107,20
@@
RS <- RS + 1
print(RS)
"""
print(RS)
"""
+testcat = """
+RT <- (load_data[56:63] || load_data[48:55]
+ || load_data[40:47] || load_data[32:39]
+ || load_data[24:31] || load_data[16:23]
+ || load_data[8:15] || load_data[0:7])
+"""
+
+testgpr = """
+GPR(5) <- x
+"""
#code = testmul
#code = testmul
-code = testgetzero
+#code = testgetzero
+#code = testcat
+code = testgpr
#code = testreg
#code = cnttzd
#code = cmpi
#code = testreg
#code = cnttzd
#code = cmpi
diff --git
a/src/soc/decoder/pseudo/parser.py
b/src/soc/decoder/pseudo/parser.py
index 9cd669a0dec6dc2fc0c3cdf04abb073098edc891..437310ef4aa619308fd9f59d8dc836d1f00bd7bf 100644
(file)
--- a/
src/soc/decoder/pseudo/parser.py
+++ b/
src/soc/decoder/pseudo/parser.py
@@
-305,6
+305,7
@@
class PowerParser:
#p[0] = ast.Discard(p[1])
p[0] = p[1]
else:
#p[0] = ast.Discard(p[1])
p[0] = p[1]
else:
+ name = None
if isinstance(p[1], ast.Name):
name = p[1].id
elif isinstance(p[1], ast.Subscript):
if isinstance(p[1], ast.Name):
name = p[1].id
elif isinstance(p[1], ast.Subscript):
@@
-312,8
+313,16
@@
class PowerParser:
if name in self.gprs:
# add to list of uninitialised
self.uninit_regs.add(name)
if name in self.gprs:
# add to list of uninitialised
self.uninit_regs.add(name)
+ elif isinstance(p[1], ast.Call) and p[1].func.id == 'GPR':
+ print(astor.dump_tree(p[1]))
+ # replace GPR(x) with GPR[x]
+ idx = p[1].args[0]
+ p[1] = ast.Subscript(p[1].func, idx)
+ else:
+ print ("help, help")
+ print(astor.dump_tree(p[1]))
print("expr assign", name, p[1])
print("expr assign", name, p[1])
- if name in self.gprs:
+ if name
and name
in self.gprs:
self.write_regs.add(name) # add to list of regs to write
p[0] = Assign(p[1], p[3])
self.write_regs.add(name) # add to list of regs to write
p[0] = Assign(p[1], p[3])
diff --git
a/src/soc/decoder/pseudo/pywriter.py
b/src/soc/decoder/pseudo/pywriter.py
index ddc4dc59edaa5c1710512e85e7f0dbbc47bf229d..2bc9dc5e27fbeb26a04482094c00653e72bb84fd 100644
(file)
--- a/
src/soc/decoder/pseudo/pywriter.py
+++ b/
src/soc/decoder/pseudo/pywriter.py
@@
-79,5
+79,7
@@
class PyISAWriter(ISA):
if __name__ == '__main__':
isa = PyISAWriter()
if __name__ == '__main__':
isa = PyISAWriter()
+ isa.write_pysource('fixedload')
+ exit(0)
isa.write_pysource('comparefixed')
isa.write_pysource('fixedarith')
isa.write_pysource('comparefixed')
isa.write_pysource('fixedarith')