+## CR Weird group
+
+Outlined in [[sv/cr_int_predication]] these instructions massively save on CR-Field
+instruction count. Multi-bit to single-bit and vice-versa normally requiring several
+CR-ops (crand, crxor) are done in one single instruction. The reason for their
+addition is down to SVP64 overloading CR Fields as Vector Predicate Masks.
+Reducing instruction count in hot-loops is considered high priority.
+
+An additional need is to do popcount on CR Field bit vectors but adding such instructions
+to the *Condition Register* side was deemed to be far too much. Therefore, priority
+was giiven instead to transferring several CR Field bits into GPRs, whereupon
+the full set of tandard Scalar GPR Logical Operations may be used. This strategy
+has the side-effect of keeping the CRweird group down to only five instructions.
+
+