projects
/
libreriscv.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
1342831
)
(no commit message)
author
higuoxing
<higuoxing@web>
Tue, 3 Apr 2018 02:15:44 +0000
(
03:15
+0100)
committer
IkiWiki
<ikiwiki.info>
Tue, 3 Apr 2018 02:15:44 +0000
(
03:15
+0100)
shakti/m_class/pinmux.mdwn
patch
|
blob
|
history
diff --git
a/shakti/m_class/pinmux.mdwn
b/shakti/m_class/pinmux.mdwn
index 58752bb61aad425760391c3fe64fd11424468791..79261c51b1057dd22dd6545ab076ee8a718e72bb 100644
(file)
--- a/
shakti/m_class/pinmux.mdwn
+++ b/
shakti/m_class/pinmux.mdwn
@@
-63,10
+63,6
@@
Introductions:
and currently responsible for coordinating the design of a fully Libre
RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
not much experience at verilog (have done a couple of tutorials).
and currently responsible for coordinating the design of a fully Libre
RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
not much experience at verilog (have done a couple of tutorials).
-* Xing GUO(xing) - undergraduate (3rd year) from Southeast
- University, EE student, C/C++, Python, Verilog, assembly (not very proficient),
- Haskell (not very proficient). RTL design, server maintenance.
- E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
* Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
* Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)