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give names to muxer submodules
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 3 Aug 2019 09:49:31 +0000
(10:49 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 3 Aug 2019 09:49:31 +0000
(10:49 +0100)
src/nmutil/multipipe.py
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diff --git
a/src/nmutil/multipipe.py
b/src/nmutil/multipipe.py
index 14d532d38c11fbfa51b8c25ff9f668267814b8ce..c0d9127c37b8feab0ed79a1e4033e7a5d06b1f38 100644
(file)
--- a/
src/nmutil/multipipe.py
+++ b/
src/nmutil/multipipe.py
@@
-180,7
+180,7
@@
class CombMultiOutPipeline(MultiOutControlBase):
m = MultiOutControlBase.elaborate(self, platform)
if hasattr(self.n_mux, "elaborate"): # TODO: identify submodule?
m = MultiOutControlBase.elaborate(self, platform)
if hasattr(self.n_mux, "elaborate"): # TODO: identify submodule?
- m.submodules
+
= self.n_mux
+ m.submodules
.n_mux
= self.n_mux
# need buffer register conforming to *input* spec
r_data = _spec(self.stage.ispec, 'r_data') # input type
# need buffer register conforming to *input* spec
r_data = _spec(self.stage.ispec, 'r_data') # input type
@@
-260,7
+260,7
@@
class CombMultiInPipeline(MultiInControlBase):
def elaborate(self, platform):
m = MultiInControlBase.elaborate(self, platform)
def elaborate(self, platform):
m = MultiInControlBase.elaborate(self, platform)
- m.submodules
+
= self.p_mux
+ m.submodules
.p_mux
= self.p_mux
# need an array of buffer registers conforming to *input* spec
r_data = []
# need an array of buffer registers conforming to *input* spec
r_data = []