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xilinx mig: put a buffer infront of the controller (#13)
author
Wesley W. Terpstra
<wesley@sifive.com>
Thu, 11 May 2017 18:50:07 +0000
(11:50 -0700)
committer
GitHub
<noreply@github.com>
Thu, 11 May 2017 18:50:07 +0000
(11:50 -0700)
This makes placement of the L2 and DDR controller easier.
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