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Show some usage of PortInterface in action
author
Cesar Strauss
<cestrauss@gmail.com>
Sat, 10 Jul 2021 21:53:22 +0000
(18:53 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Sat, 10 Jul 2021 21:53:22 +0000
(18:53 -0300)
src/soc/simple/test/test_runner.py
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diff --git
a/src/soc/simple/test/test_runner.py
b/src/soc/simple/test/test_runner.py
index cb4ca4589719d3fb09a214dd2e1cc15711f0c4cd..342a7ee0720fca4a6c7d2591556289c049417df8 100644
(file)
--- a/
src/soc/simple/test/test_runner.py
+++ b/
src/soc/simple/test/test_runner.py
@@
-414,6
+414,17
@@
class TestRunner(FHDLTestCase):
'core.int.rp_src1.memory(9)[63:0]',
'core.int.rp_src1.memory(10)[63:0]',
'core.int.rp_src1.memory(13)[63:0]',
'core.int.rp_src1.memory(9)[63:0]',
'core.int.rp_src1.memory(10)[63:0]',
'core.int.rp_src1.memory(13)[63:0]',
+ {'comment': 'memory port interface'},
+ 'core.l0.pimem.ldst_port0_is_ld_i',
+ 'core.l0.pimem.ldst_port0_is_st_i',
+ 'core.l0.pimem.ldst_port0_busy_o',
+ 'core.l0.pimem.ldst_port0_addr_i[47:0]',
+ 'core.l0.pimem.ldst_port0_addr_i_ok',
+ 'core.l0.pimem.ldst_port0_addr_ok_o',
+ 'core.l0.pimem.ldst_port0_st_data_i[63:0]',
+ 'core.l0.pimem.ldst_port0_st_data_i_ok',
+ 'core.l0.pimem.ldst_port0_ld_data_o[63:0]',
+ 'core.l0.pimem.ldst_port0_ld_data_o_ok'
]
if self.microwatt_mmu:
]
if self.microwatt_mmu: