+More advanced features add predication, element-width overrides, and
+Vertical-First Mode.
+
+**Definition of SVP64 Prefixing:**
+
+SVP64 is a well-defined implementation of the Simple-V Loop/Vector concept,
+in a 32-bit Prefix format, that exploits the following instruction
+(the Defined Word) using it as a "template". It requires 24 bits,
+some of which are common to all Suffixes, and some Mode bits are specific
+to the Defined Word class: Load/Store-Immediate, Load/Store-Indexed,
+Arithmetic/Logical, Condition Register operations, and Branch-Conditional.
+Anything not falling into those five categories is termed "UnVectoriseable".