rename InternalOp to MicrOp

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index d6b191f07cc32e756ae4c6e06bb66171a415959f..8141e2f78214d146c840fd0947d9bd328ddb28f5 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -5,7 +5,7 @@ based on Anton Blanchard microwatt decode2.vhdl
 """
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
 """
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject

-from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR, LDSTMode
+from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode

 
 
 class Data(Record):
 
 
 class Data(Record):


@@ -29,7 +29,7 @@ class Decode2ToOperand(RecordObject):
 
         RecordObject.__init__(self, name=name)
 
 
         RecordObject.__init__(self, name=name)
 

-        self.insn_type = Signal(InternalOp, reset_less=True)
+        self.insn_type = Signal(MicrOp, reset_less=True)

         self.fn_unit = Signal(Function, reset_less=True)
         self.imm_data = Data(64, name="imm")
 
         self.fn_unit = Signal(Function, reset_less=True)
         self.imm_data = Data(64, name="imm")
 

diff --git a/src/soc/decoder/formal/proof_decoder.py b/src/soc/decoder/formal/proof_decoder.py
index e1d793eafbe083c9a1b98ccc656d897926329c4b..5abd9182ecf6e42ad6035e1a521edcca732bfd36 100644 (file)
--- a/src/soc/decoder/formal/proof_decoder.py
+++ b/src/soc/decoder/formal/proof_decoder.py
@@ -6,7 +6,7 @@ from soc.decoder.power_decoder import create_pdecode, PowerOp
 from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, Form, Function,
                                      LdstLen, CryIn,
 from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, Form, Function,
                                      LdstLen, CryIn,

-                                     InternalOp, SPR, get_csv)
+                                     MicrOp, SPR, get_csv)

 from soc.decoder.power_decoder2 import (PowerDecode2,
                                         Decode2ToExecute1Type)
 import unittest
 from soc.decoder.power_decoder2 import (PowerDecode2,
                                         Decode2ToExecute1Type)
 import unittest


@@ -60,7 +60,7 @@ class Driver(Elaboratable):
                         self.comb += self.assert_dec1_signals(dec1, row)
                 with self.m.Default():
                     self.comb += Assert(dec.op.internal_op ==
                         self.comb += self.assert_dec1_signals(dec1, row)
                 with self.m.Default():
                     self.comb += Assert(dec.op.internal_op ==

-                                        InternalOp.OP_ILLEGAL)
+                                        MicrOp.OP_ILLEGAL)

                                         
 
     def handle_subdecoders(self, dec1, decoders):
                                         
 
     def handle_subdecoders(self, dec1, decoders):


@@ -75,7 +75,7 @@ class Driver(Elaboratable):
     def assert_dec1_signals(self, dec, row):
         op = dec.op
         return [Assert(op.function_unit == Function[row['unit']]),
     def assert_dec1_signals(self, dec, row):
         op = dec.op
         return [Assert(op.function_unit == Function[row['unit']]),

-                Assert(op.internal_op == InternalOp[row['internal op']]),
+                Assert(op.internal_op == MicrOp[row['internal op']]),

                 Assert(op.in1_sel == In1Sel[row['in1']]),
                 Assert(op.in2_sel == In2Sel[row['in2']]),
                 Assert(op.in3_sel == In3Sel[row['in3']]),
                 Assert(op.in1_sel == In1Sel[row['in1']]),
                 Assert(op.in2_sel == In2Sel[row['in2']]),
                 Assert(op.in3_sel == In3Sel[row['in3']]),

diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py
index b19588f6bca30fe729712c2a4d590811a1251de2..195044738bd693777a00b025e65e16d6d356eaf2 100644 (file)
--- a/src/soc/decoder/formal/proof_decoder2.py
+++ b/src/soc/decoder/formal/proof_decoder2.py
@@ -5,7 +5,7 @@ from nmutil.formaltest import FHDLTestCase
 from soc.decoder.power_decoder import create_pdecode, PowerOp
 from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, Form,
 from soc.decoder.power_decoder import create_pdecode, PowerOp
 from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, Form,

-                                     InternalOp, SPR)
+                                     MicrOp, SPR)

 from soc.decoder.power_decoder2 import (PowerDecode2,
                                         Decode2ToExecute1Type)
 import unittest
 from soc.decoder.power_decoder2 import (PowerDecode2,
                                         Decode2ToExecute1Type)
 import unittest


@@ -53,13 +53,13 @@ class Driver(Elaboratable):
                 comb += Assert(pdecode2.e.read_reg1.data == ra)
                 comb += Assert(pdecode2.e.read_reg1.ok == 1)
                 op = pdecode.op.internal_op
                 comb += Assert(pdecode2.e.read_reg1.data == ra)
                 comb += Assert(pdecode2.e.read_reg1.ok == 1)
                 op = pdecode.op.internal_op

-        with m.If((op == InternalOp.OP_BC) |
-                  (op == InternalOp.OP_BCREG)):
+        with m.If((op == MicrOp.OP_BC) |
+                  (op == MicrOp.OP_BCREG)):

             with m.If(~self.instr_bits(8)):
                 comb += Assert(pdecode2.e.read_spr1.data == SPR.CTR)
                 comb += Assert(pdecode2.e.read_spr1.ok == 1)
             with m.If(~self.instr_bits(8)):
                 comb += Assert(pdecode2.e.read_spr1.data == SPR.CTR)
                 comb += Assert(pdecode2.e.read_spr1.ok == 1)

-        with m.If((op == InternalOp.OP_MFSPR) |
-                  (op == InternalOp.OP_MTSPR)):
+        with m.If((op == MicrOp.OP_MFSPR) |
+                  (op == MicrOp.OP_MTSPR)):

             comb += Assert(pdecode2.e.read_spr1.data == self.instr_bits(11, 20))
             comb += Assert(pdecode2.e.read_spr1.ok == 1)
 
             comb += Assert(pdecode2.e.read_spr1.data == self.instr_bits(11, 20))
             comb += Assert(pdecode2.e.read_spr1.ok == 1)
 

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index aeeaa5d5da219d04c85f70d74ba20343c1a23676..e5fdfc5a526190764e71d00cb26fd0eda4b87390 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -14,7 +14,7 @@ from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,

-                                     insns, InternalOp)
+                                     insns, MicrOp)

 from soc.decoder.helpers import exts
 from soc.consts import PI, MSR
 
 from soc.decoder.helpers import exts
 from soc.consts import PI, MSR
 


@@ -515,7 +515,7 @@ class ISACaller:
         rc_ok = yield self.dec2.e.do.rc.ok
         # grrrr have to special-case MUL op (see DecodeOE)
         print ("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op)
         rc_ok = yield self.dec2.e.do.rc.ok
         # grrrr have to special-case MUL op (see DecodeOE)
         print ("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op)

-        if int_op in [InternalOp.OP_MUL_H64.value, InternalOp.OP_MUL_H32.value]:
+        if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:

             print ("mul op")
             if rc_en & rc_ok:
                 asmop += "."
             print ("mul op")
             if rc_en & rc_ok:
                 asmop += "."


@@ -526,12 +526,12 @@ class ISACaller:
         if lk:
             asmop += "l"
         print ("int_op", int_op)
         if lk:
             asmop += "l"
         print ("int_op", int_op)

-        if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]:
+        if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:

             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
             print ("AA", AA)
             if AA:
                 asmop += "a"
             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
             print ("AA", AA)
             if AA:
                 asmop += "a"

-        if int_op == InternalOp.OP_MFCR.value:
+        if int_op == MicrOp.OP_MFCR.value:

             dec_insn = yield self.dec2.e.do.insn
             if dec_insn & (1<<20) != 0: # sigh
                 asmop = 'mfocrf'
             dec_insn = yield self.dec2.e.do.insn
             if dec_insn & (1<<20) != 0: # sigh
                 asmop = 'mfocrf'


@@ -539,7 +539,7 @@ class ISACaller:
                 asmop = 'mfcr'
         # XXX TODO: for whatever weird reason this doesn't work
         # https://bugs.libre-soc.org/show_bug.cgi?id=390
                 asmop = 'mfcr'
         # XXX TODO: for whatever weird reason this doesn't work
         # https://bugs.libre-soc.org/show_bug.cgi?id=390

-        if int_op == InternalOp.OP_MTCRF.value:
+        if int_op == MicrOp.OP_MTCRF.value:

             dec_insn = yield self.dec2.e.do.insn
             if dec_insn & (1<<20) != 0: # sigh
                 asmop = 'mtocrf'
             dec_insn = yield self.dec2.e.do.insn
             if dec_insn & (1<<20) != 0: # sigh
                 asmop = 'mtocrf'

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index c93ee5189cdcab26849c523355a2f26fcac2147c..b0ad17b2fe0b3c13522cdb9dad046e11892bdb65 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -82,7 +82,7 @@ Top Level:
 from collections import namedtuple
 from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from collections import namedtuple
 from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil

-from soc.decoder.power_enums import (Function, Form, InternalOp,
+from soc.decoder.power_enums import (Function, Form, MicrOp,

                                      In1Sel, In2Sel, In3Sel, OutSel,
                                      RC, LdstLen, LDSTMode, CryIn, get_csv,
                                      single_bit_flags, CRInSel,
                                      In1Sel, In2Sel, In3Sel, OutSel,
                                      RC, LdstLen, LDSTMode, CryIn, get_csv,
                                      single_bit_flags, CRInSel,


@@ -117,7 +117,7 @@ class PowerOp:
 
     def __init__(self, incl_asm=True):
         self.function_unit = Signal(Function, reset_less=True)
 
     def __init__(self, incl_asm=True):
         self.function_unit = Signal(Function, reset_less=True)

-        self.internal_op = Signal(InternalOp, reset_less=True)
+        self.internal_op = Signal(MicrOp, reset_less=True)

         self.form = Signal(Form, reset_less=True)
         if incl_asm: # for simulator only
             self.asmcode = Signal(8, reset_less=True)
         self.form = Signal(Form, reset_less=True)
         if incl_asm: # for simulator only
             self.asmcode = Signal(8, reset_less=True)


@@ -156,7 +156,7 @@ class PowerOp:
             ldst_mode = LDSTMode[ldst_mode]
         res = [self.function_unit.eq(Function[row['unit']]),
                self.form.eq(Form[row['form']]),
             ldst_mode = LDSTMode[ldst_mode]
         res = [self.function_unit.eq(Function[row['unit']]),
                self.form.eq(Form[row['form']]),

-               self.internal_op.eq(InternalOp[row['internal op']]),
+               self.internal_op.eq(MicrOp[row['internal op']]),

                self.in1_sel.eq(In1Sel[row['in1']]),
                self.in2_sel.eq(In2Sel[row['in2']]),
                self.in3_sel.eq(In3Sel[row['in3']]),
                self.in1_sel.eq(In1Sel[row['in1']]),
                self.in2_sel.eq(In2Sel[row['in2']]),
                self.in3_sel.eq(In3Sel[row['in3']]),

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 615f78f7e10bf2cb9421fdedbd71ef4586324018..eba6c71d713d9bbda24a1e252da63d3e444ba08f 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -15,7 +15,7 @@ from nmutil.extend import exts
 from soc.decoder.power_regspec_map import regspec_decode_read
 from soc.decoder.power_regspec_map import regspec_decode_write
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_regspec_map import regspec_decode_read
 from soc.decoder.power_regspec_map import regspec_decode_write
 from soc.decoder.power_decoder import create_pdecode

-from soc.decoder.power_enums import (InternalOp, CryIn, Function,
+from soc.decoder.power_enums import (MicrOp, CryIn, Function,

                                      CRInSel, CROutSel,
                                      LdstLen, In1Sel, In2Sel, In3Sel,
                                      OutSel, SPR, RC)
                                      CRInSel, CROutSel,
                                      LdstLen, In1Sel, In2Sel, In3Sel,
                                      OutSel, SPR, RC)


@@ -41,12 +41,12 @@ def instr_is_priv(m, op, insn):
     comb = m.d.comb
     Signal = is_priv_insn(reset_less=True)
     with m.Switch(op):
     comb = m.d.comb
     Signal = is_priv_insn(reset_less=True)
     with m.Switch(op):

-        with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
-        with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
-        with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
-        with m.Case(InternalOp.OP_MTMSR): comb += is_priv_insn.eq(1)
-        with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
-        with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_MTMSR): comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_RFID)  : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)

     with m.If(op == OP_MFSPR | op == OP_MTSPR):
         with m.If(insn[20]): # field XFX.spr[-1] i think
             comb += is_priv_insn.eq(1)
     with m.If(op == OP_MFSPR | op == OP_MTSPR):
         with m.If(insn[20]): # field XFX.spr[-1] i think
             comb += is_priv_insn.eq(1)


@@ -112,11 +112,11 @@ class DecodeA(Elaboratable):
         # decode Fast-SPR based on instruction type
         op = self.dec.op
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
         # decode Fast-SPR based on instruction type
         op = self.dec.op
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut

-        with m.If(op.internal_op == InternalOp.OP_BC):
+        with m.If(op.internal_op == MicrOp.OP_BC):

             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)

-        with m.Elif(op.internal_op == InternalOp.OP_BCREG):
+        with m.Elif(op.internal_op == MicrOp.OP_BCREG):

             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
             with m.If(xo9 & ~xo5):
             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
             with m.If(xo9 & ~xo5):


@@ -124,7 +124,7 @@ class DecodeA(Elaboratable):
                 comb += self.fast_out.ok.eq(1)
 
         # MFSPR move from SPRs
                 comb += self.fast_out.ok.eq(1)
 
         # MFSPR move from SPRs

-        with m.If(op.internal_op == InternalOp.OP_MFSPR):
+        with m.If(op.internal_op == MicrOp.OP_MFSPR):

             spr = Signal(10, reset_less=True)
             comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
             with m.Switch(spr):
             spr = Signal(10, reset_less=True)
             comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
             with m.Switch(spr):


@@ -224,7 +224,7 @@ class DecodeB(Elaboratable):
         op = self.dec.op
         # BCREG implicitly uses LR or TAR for 2nd reg
         # CTR however is already in fast_spr1 *not* 2.
         op = self.dec.op
         # BCREG implicitly uses LR or TAR for 2nd reg
         # CTR however is already in fast_spr1 *not* 2.

-        with m.If(op.internal_op == InternalOp.OP_BCREG):
+        with m.If(op.internal_op == MicrOp.OP_BCREG):

             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
             with m.If(~xo9):
             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
             with m.If(~xo9):


@@ -297,7 +297,7 @@ class DecodeOut(Elaboratable):
                 spr = Signal(10, reset_less=True)
                 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
                 # TODO MTSPR 1st spr (fast)
                 spr = Signal(10, reset_less=True)
                 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
                 # TODO MTSPR 1st spr (fast)

-                with m.If(op.internal_op == InternalOp.OP_MTSPR):
+                with m.If(op.internal_op == MicrOp.OP_MTSPR):

                     with m.Switch(spr):
                         # fast SPRs
                         with m.Case(SPR.CTR.value):
                     with m.Switch(spr):
                         # fast SPRs
                         with m.Case(SPR.CTR.value):


@@ -326,14 +326,14 @@ class DecodeOut(Elaboratable):
 
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
         op = self.dec.op
 
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
         op = self.dec.op

-        with m.If((op.internal_op == InternalOp.OP_BC) |
-                  (op.internal_op == InternalOp.OP_BCREG)):
+        with m.If((op.internal_op == MicrOp.OP_BC) |
+                  (op.internal_op == MicrOp.OP_BCREG)):

             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
 
         # RFID 1st spr (fast)
             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
 
         # RFID 1st spr (fast)

-        with m.If(op.internal_op == InternalOp.OP_RFID):
+        with m.If(op.internal_op == MicrOp.OP_RFID):

             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += self.fast_out.ok.eq(1)
 
             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += self.fast_out.ok.eq(1)
 


@@ -366,15 +366,15 @@ class DecodeOut2(Elaboratable):
         # B, BC or BCREG: potential implicit register (LR) output
         # these give bl, bcl, bclrl, etc.
         op = self.dec.op
         # B, BC or BCREG: potential implicit register (LR) output
         # these give bl, bcl, bclrl, etc.
         op = self.dec.op

-        with m.If((op.internal_op == InternalOp.OP_BC) |
-                  (op.internal_op == InternalOp.OP_B) |
-                  (op.internal_op == InternalOp.OP_BCREG)):
+        with m.If((op.internal_op == MicrOp.OP_BC) |
+                  (op.internal_op == MicrOp.OP_B) |
+                  (op.internal_op == MicrOp.OP_BCREG)):

             with m.If(self.lk): # "link" mode
                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
                 comb += self.fast_out.ok.eq(1)
 
         # RFID 2nd spr (fast)
             with m.If(self.lk): # "link" mode
                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
                 comb += self.fast_out.ok.eq(1)
 
         # RFID 2nd spr (fast)

-        with m.If(op.internal_op == InternalOp.OP_RFID):
+        with m.If(op.internal_op == MicrOp.OP_RFID):

                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
                 comb += self.fast_out.ok.eq(1)
 
                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
                 comb += self.fast_out.ok.eq(1)
 


@@ -433,8 +433,8 @@ class DecodeOE(Elaboratable):
         comb = m.d.comb
         op = self.dec.op
 
         comb = m.d.comb
         op = self.dec.op
 

-        with m.If((op.internal_op == InternalOp.OP_MUL_H64) |
-                  (op.internal_op == InternalOp.OP_MUL_H32)):
+        with m.If((op.internal_op == MicrOp.OP_MUL_H64) |
+                  (op.internal_op == MicrOp.OP_MUL_H32)):

             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
             pass
         with m.Else():
             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
             pass
         with m.Else():


@@ -653,27 +653,27 @@ class PowerDecode2(Elaboratable):
         # sigh this is exactly the sort of thing for which the
         # decoder is designed to not need.  MTSPR, MFSPR and others need
         # access to the XER bits.  however setting e.oe is not appropriate
         # sigh this is exactly the sort of thing for which the
         # decoder is designed to not need.  MTSPR, MFSPR and others need
         # access to the XER bits.  however setting e.oe is not appropriate

-        with m.If(op.internal_op == InternalOp.OP_MFSPR):
+        with m.If(op.internal_op == MicrOp.OP_MFSPR):

             comb += e.xer_in.eq(1)
             comb += e.xer_in.eq(1)

-        with m.If(op.internal_op == InternalOp.OP_MTSPR):
+        with m.If(op.internal_op == MicrOp.OP_MTSPR):

             comb += e.xer_out.eq(1)
 
         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
             comb += e.xer_out.eq(1)
 
         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation

-        with m.If(op.internal_op == InternalOp.OP_TRAP):
+        with m.If(op.internal_op == MicrOp.OP_TRAP):

             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 
         # illegal instruction must redirect to trap. this is done by
         # *overwriting* the decoded instruction and starting again.
         # (note: the same goes for interrupts and for privileged operations,
         # just with different trapaddr and traptype)
             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 
         # illegal instruction must redirect to trap. this is done by
         # *overwriting* the decoded instruction and starting again.
         # (note: the same goes for interrupts and for privileged operations,
         # just with different trapaddr and traptype)

-        with m.If(op.internal_op == InternalOp.OP_ILLEGAL):
+        with m.If(op.internal_op == MicrOp.OP_ILLEGAL):

             # illegal instruction trap
             self.trap(m, TT_ILLEG, 0x700)
 
         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
         # Note: OP_SC could actually be modified to just be a trap
             # illegal instruction trap
             self.trap(m, TT_ILLEG, 0x700)
 
         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
         # Note: OP_SC could actually be modified to just be a trap

-        with m.If((do.insn_type == InternalOp.OP_TRAP) |
-                  (do.insn_type == InternalOp.OP_SC)):
+        with m.If((do.insn_type == MicrOp.OP_TRAP) |
+                  (do.insn_type == MicrOp.OP_SC)):

             # TRAP write fast1 = SRR0
             comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += e.write_fast1.ok.eq(1)
             # TRAP write fast1 = SRR0
             comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += e.write_fast1.ok.eq(1)


@@ -682,7 +682,7 @@ class PowerDecode2(Elaboratable):
             comb += e.write_fast2.ok.eq(1)
 
         # RFID: needs to read SRR0/1
             comb += e.write_fast2.ok.eq(1)
 
         # RFID: needs to read SRR0/1

-        with m.If(do.insn_type == InternalOp.OP_RFID):
+        with m.If(do.insn_type == MicrOp.OP_RFID):

             # TRAP read fast1 = SRR0
             comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += e.read_fast1.ok.eq(1)
             # TRAP read fast1 = SRR0
             comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += e.read_fast1.ok.eq(1)


@@ -706,7 +706,7 @@ class PowerDecode2(Elaboratable):
         comb += e.eq(0) # reset eeeeeverything
         # start again
         comb += do.insn.eq(self.dec.opcode_in)
         comb += e.eq(0) # reset eeeeeverything
         # start again
         comb += do.insn.eq(self.dec.opcode_in)

-        comb += do.insn_type.eq(InternalOp.OP_TRAP)
+        comb += do.insn_type.eq(MicrOp.OP_TRAP)

         comb += do.fn_unit.eq(Function.TRAP)
         comb += do.trapaddr.eq(trapaddr >> 4) # cut bottom 4 bits
         comb += do.traptype.eq(traptype) # request type
         comb += do.fn_unit.eq(Function.TRAP)
         comb += do.trapaddr.eq(trapaddr >> 4) # cut bottom 4 bits
         comb += do.traptype.eq(traptype) # request type

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 92b7101ced8cd315ae98b6605e4d64dbf824ddaf..817bbd19ac98626c0b19c18869e65fbde68e9d06 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -132,7 +132,7 @@ for i, insn in enumerate(_insns):
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique

-class InternalOp(Enum):
+class MicrOp(Enum):

     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
     OP_NOP = 1
     OP_ADD = 2
     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
     OP_NOP = 1
     OP_ADD = 2

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 80206db4a3cd3528219d7272f9e310edcf90a28f..72d05a79173bb3b396e6ceb9e34e288b60a0f2d2 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,


@@ -39,12 +39,12 @@ class Checker:
 class RegRegOp:
     def __init__(self):
         self.ops = {
 class RegRegOp:
     def __init__(self):
         self.ops = {

-            "add": InternalOp.OP_ADD,
-            "and": InternalOp.OP_AND,
-            "or": InternalOp.OP_OR,
-            "add.": InternalOp.OP_ADD,
-            "lwzx": InternalOp.OP_LOAD,
-            "stwx": InternalOp.OP_STORE,
+            "add": MicrOp.OP_ADD,
+            "and": MicrOp.OP_AND,
+            "or": MicrOp.OP_OR,
+            "add.": MicrOp.OP_ADD,
+            "lwzx": MicrOp.OP_LOAD,
+            "stwx": MicrOp.OP_STORE,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -60,7 +60,7 @@ class RegRegOp:
         return string
 
     def check_results(self, pdecode2):
         return string
 
     def check_results(self, pdecode2):

-        if self.opcode == InternalOp.OP_STORE:
+        if self.opcode == MicrOp.OP_STORE:

             r1sel = yield pdecode2.e.read_reg3.data
         else:
             r1sel = yield pdecode2.e.write_reg.data
             r1sel = yield pdecode2.e.read_reg3.data
         else:
             r1sel = yield pdecode2.e.write_reg.data


@@ -92,10 +92,10 @@ class RegImmOp(Checker):
     def __init__(self):
         super().__init__()
         self.ops = {
     def __init__(self):
         super().__init__()
         self.ops = {

-            "addi": InternalOp.OP_ADD,
-            "addis": InternalOp.OP_ADD,
-            "andi.": InternalOp.OP_AND,
-            "ori": InternalOp.OP_OR,
+            "addi": MicrOp.OP_ADD,
+            "addis": MicrOp.OP_ADD,
+            "andi.": MicrOp.OP_AND,
+            "ori": MicrOp.OP_OR,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -140,14 +140,14 @@ class LdStOp(Checker):
     def __init__(self):
         super().__init__()
         self.ops = {
     def __init__(self):
         super().__init__()
         self.ops = {

-            "lwz": InternalOp.OP_LOAD,
-            "stw": InternalOp.OP_STORE,
-            "lwzu": InternalOp.OP_LOAD,
-            "stwu": InternalOp.OP_STORE,
-            "lbz": InternalOp.OP_LOAD,
-            "lhz": InternalOp.OP_LOAD,
-            "stb": InternalOp.OP_STORE,
-            "sth": InternalOp.OP_STORE,
+            "lwz": MicrOp.OP_LOAD,
+            "stw": MicrOp.OP_STORE,
+            "lwzu": MicrOp.OP_LOAD,
+            "stwu": MicrOp.OP_STORE,
+            "lbz": MicrOp.OP_LOAD,
+            "lhz": MicrOp.OP_LOAD,
+            "stb": MicrOp.OP_STORE,
+            "sth": MicrOp.OP_STORE,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -167,7 +167,7 @@ class LdStOp(Checker):
     def check_results(self, pdecode2):
         print("Check")
         r2sel = yield pdecode2.e.read_reg1.data
     def check_results(self, pdecode2):
         print("Check")
         r2sel = yield pdecode2.e.read_reg1.data

-        if self.opcode == InternalOp.OP_STORE:
+        if self.opcode == MicrOp.OP_STORE:

             r1sel = yield pdecode2.e.read_reg3.data
         else:
             r1sel = yield pdecode2.e.write_reg.data
             r1sel = yield pdecode2.e.read_reg3.data
         else:
             r1sel = yield pdecode2.e.write_reg.data


@@ -198,7 +198,7 @@ class LdStOp(Checker):
 class CmpRegOp:
     def __init__(self):
         self.ops = {
 class CmpRegOp:
     def __init__(self):
         self.ops = {

-            "cmp": InternalOp.OP_CMP,
+            "cmp": MicrOp.OP_CMP,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -226,12 +226,12 @@ class CmpRegOp:
 class RotateOp:
     def __init__(self):
         self.ops = {
 class RotateOp:
     def __init__(self):
         self.ops = {

-            "rlwinm": InternalOp.OP_CMP,
-            "rlwnm": InternalOp.OP_CMP,
-            "rlwimi": InternalOp.OP_CMP,
-            "rlwinm.": InternalOp.OP_CMP,
-            "rlwnm.": InternalOp.OP_CMP,
-            "rlwimi.": InternalOp.OP_CMP,
+            "rlwinm": MicrOp.OP_CMP,
+            "rlwnm": MicrOp.OP_CMP,
+            "rlwimi": MicrOp.OP_CMP,
+            "rlwinm.": MicrOp.OP_CMP,
+            "rlwnm.": MicrOp.OP_CMP,
+            "rlwimi.": MicrOp.OP_CMP,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -278,10 +278,10 @@ class RotateOp:
 class Branch:
     def __init__(self):
         self.ops = {
 class Branch:
     def __init__(self):
         self.ops = {

-            "b": InternalOp.OP_B,
-            "bl": InternalOp.OP_B,
-            "ba": InternalOp.OP_B,
-            "bla": InternalOp.OP_B,
+            "b": MicrOp.OP_B,
+            "bl": MicrOp.OP_B,
+            "ba": MicrOp.OP_B,
+            "bla": MicrOp.OP_B,

         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]
         }
         self.opcodestr = random.choice(list(self.ops.keys()))
         self.opcode = self.ops[self.opcodestr]


@@ -311,10 +311,10 @@ class Branch:
 class BranchCond:
     def __init__(self):
         self.ops = {
 class BranchCond:
     def __init__(self):
         self.ops = {

-            "bc": InternalOp.OP_B,
-            "bcl": InternalOp.OP_B,
-            "bca": InternalOp.OP_B,
-            "bcla": InternalOp.OP_B,
+            "bc": MicrOp.OP_B,
+            "bcl": MicrOp.OP_B,
+            "bca": MicrOp.OP_B,
+            "bcla": MicrOp.OP_B,

         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual
         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual


@@ -360,10 +360,10 @@ class BranchCond:
 class BranchRel:
     def __init__(self):
         self.ops = {
 class BranchRel:
     def __init__(self):
         self.ops = {

-            "bclr": InternalOp.OP_B,
-            "bcctr": InternalOp.OP_B,
-            "bclrl": InternalOp.OP_B,
-            "bcctrl": InternalOp.OP_B,
+            "bclr": MicrOp.OP_B,
+            "bcctr": MicrOp.OP_B,
+            "bclrl": MicrOp.OP_B,
+            "bcctrl": MicrOp.OP_B,

         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual
         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual


@@ -403,7 +403,7 @@ class BranchRel:
 class CROp:
     def __init__(self):
         self.ops = {
 class CROp:
     def __init__(self):
         self.ops = {

-            "crand": InternalOp.OP_CROP,
+            "crand": MicrOp.OP_CROP,

         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual
         }
         # Given in Figure 40 "BO field encodings" in section 2.4, page
         # 33 of the Power ISA v3.0B manual

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index a03589c359fdce3c2914f5681cb6897305f3b236..24da6f444b5421409fb953d4313a27b28dc1f10f 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -5,7 +5,7 @@ from nmigen.cli import rtlil
 import os
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 import os
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      CRInSel, CROutSel,
                                      OutSel, RC, LdstLen, CryIn,
                                      In1Sel, In2Sel, In3Sel,
                                      CRInSel, CROutSel,
                                      OutSel, RC, LdstLen, CryIn,


@@ -20,7 +20,7 @@ class DecoderTestCase(FHDLTestCase):
         comb = m.d.comb
         opcode = Signal(32)
         function_unit = Signal(Function)
         comb = m.d.comb
         opcode = Signal(32)
         function_unit = Signal(Function)

-        internal_op = Signal(InternalOp)
+        internal_op = Signal(MicrOp)

         in1_sel = Signal(In1Sel)
         in2_sel = Signal(In2Sel)
         in3_sel = Signal(In3Sel)
         in1_sel = Signal(In1Sel)
         in2_sel = Signal(In2Sel)
         in3_sel = Signal(In3Sel)


@@ -76,7 +76,7 @@ class DecoderTestCase(FHDLTestCase):
 
                 yield Delay(1e-6)
                 signals = [(function_unit, Function, 'unit'),
 
                 yield Delay(1e-6)
                 signals = [(function_unit, Function, 'unit'),

-                           (internal_op, InternalOp, 'internal op'),
+                           (internal_op, MicrOp, 'internal op'),

                            (in1_sel, In1Sel, 'in1'),
                            (in2_sel, In2Sel, 'in2'),
                            (in3_sel, In3Sel, 'in3'),
                            (in1_sel, In1Sel, 'in1'),
                            (in2_sel, In2Sel, 'in2'),
                            (in3_sel, In3Sel, 'in3'),

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index c1ca6fa315ed0f603ce9ded499c0e76f1eb25860..90838b269a95705541d3746ca56c7231a3011d21 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -16,7 +16,7 @@ from nmigen.cli import verilog, rtlil
 from nmigen.compat.sim import run_simulation
 from nmigen.back.pysim import Simulator, Settle
 
 from nmigen.compat.sim import run_simulation
 from nmigen.back.pysim import Simulator, Settle
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.cr.cr_input_record import CompCROpSubset
 
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.cr.cr_input_record import CompCROpSubset


@@ -239,24 +239,24 @@ class ALU(Elaboratable):
             with m.If(self.p.valid_i):
 
                 # as this is a "fake" pipeline, just grab the output right now
             with m.If(self.p.valid_i):
 
                 # as this is a "fake" pipeline, just grab the output right now

-                with m.If(self.op.insn_type == InternalOp.OP_ADD):
+                with m.If(self.op.insn_type == MicrOp.OP_ADD):

                     m.d.sync += alu_r.eq(add.o)
                     m.d.sync += alu_r.eq(add.o)

-                with m.Elif(self.op.insn_type == InternalOp.OP_MUL_L64):
+                with m.Elif(self.op.insn_type == MicrOp.OP_MUL_L64):

                     m.d.sync += alu_r.eq(mul.o)
                     m.d.sync += alu_r.eq(mul.o)

-                with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
+                with m.Elif(self.op.insn_type == MicrOp.OP_SHR):

                     m.d.sync += alu_r.eq(shf.o)
                 # SUB is zero-delay, no need to register
 
                 # NOTE: all of these are fake, just something to test
 
                 # MUL, to take 5 instructions
                     m.d.sync += alu_r.eq(shf.o)
                 # SUB is zero-delay, no need to register
 
                 # NOTE: all of these are fake, just something to test
 
                 # MUL, to take 5 instructions

-                with m.If(self.op.insn_type == InternalOp.OP_MUL_L64):
+                with m.If(self.op.insn_type == MicrOp.OP_MUL_L64):

                     m.d.sync += self.counter.eq(5)
                 # SHIFT to take 1, straight away
                     m.d.sync += self.counter.eq(5)
                 # SHIFT to take 1, straight away

-                with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
+                with m.Elif(self.op.insn_type == MicrOp.OP_SHR):

                     m.d.sync += self.counter.eq(1)
                 # ADD/SUB to take 3
                     m.d.sync += self.counter.eq(1)
                 # ADD/SUB to take 3

-                with m.Elif(self.op.insn_type == InternalOp.OP_ADD):
+                with m.Elif(self.op.insn_type == MicrOp.OP_ADD):

                     m.d.sync += self.counter.eq(3)
                 # others to take no delay
                 with m.Else():
                     m.d.sync += self.counter.eq(3)
                 # others to take no delay
                 with m.Else():


@@ -417,25 +417,25 @@ def run_op(dut, a, b, op, inv_a=0):
 
 
 def alu_sim(dut):
 
 
 def alu_sim(dut):

-    result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD)
+    result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD)

     print ("alu_sim add", result)
     assert (result == 8)
 
     print ("alu_sim add", result)
     assert (result == 8)
 

-    result = yield from run_op(dut, 2, 3, InternalOp.OP_MUL_L64)
+    result = yield from run_op(dut, 2, 3, MicrOp.OP_MUL_L64)

     print ("alu_sim mul", result)
     assert (result == 6)
 
     print ("alu_sim mul", result)
     assert (result == 6)
 

-    result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD, inv_a=1)
+    result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD, inv_a=1)

     print ("alu_sim add-inv", result)
     assert (result == 65533)
 
     # test zero-delay ALU
     # don't have OP_SUB, so use any other
     print ("alu_sim add-inv", result)
     assert (result == 65533)
 
     # test zero-delay ALU
     # don't have OP_SUB, so use any other

-    result = yield from run_op(dut, 5, 3, InternalOp.OP_NOP)
+    result = yield from run_op(dut, 5, 3, MicrOp.OP_NOP)

     print ("alu_sim sub", result)
     assert (result == 2)
 
     print ("alu_sim sub", result)
     assert (result == 2)
 

-    result = yield from run_op(dut, 13, 2, InternalOp.OP_SHR)
+    result = yield from run_op(dut, 13, 2, MicrOp.OP_SHR)

     print ("alu_sim shr", result)
     assert (result == 3)
 
     print ("alu_sim shr", result)
     assert (result == 3)
 


@@ -496,21 +496,21 @@ def test_alu_parallel():
         # note that, for this test, we do not wait for the result to be ready,
         # before presenting the next input
         # 5 + 3
         # note that, for this test, we do not wait for the result to be ready,
         # before presenting the next input
         # 5 + 3

-        yield from send(5, 3, InternalOp.OP_ADD)
+        yield from send(5, 3, MicrOp.OP_ADD)

         yield
         yield
         # 2 * 3
         yield
         yield
         # 2 * 3

-        yield from send(2, 3, InternalOp.OP_MUL_L64)
+        yield from send(2, 3, MicrOp.OP_MUL_L64)

         # (-5) + 3
         # (-5) + 3

-        yield from send(5, 3, InternalOp.OP_ADD, inv_a=1)
+        yield from send(5, 3, MicrOp.OP_ADD, inv_a=1)

         yield
         # 5 - 3
         # note that this is a zero-delay operation
         yield
         # 5 - 3
         # note that this is a zero-delay operation

-        yield from send(5, 3, InternalOp.OP_NOP)
+        yield from send(5, 3, MicrOp.OP_NOP)

         yield
         yield
         # 13 >> 2
         yield
         yield
         # 13 >> 2

-        yield from send(13, 2, InternalOp.OP_SHR)
+        yield from send(13, 2, MicrOp.OP_SHR)

 
     def consumer():
         # receive and check results, interspersed with wait states
 
     def consumer():
         # receive and check results, interspersed with wait states

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 52e21f7bd1d3dd7bfcf2d5dc188db730f8774a4b..dcab911aa657e5f2fada58e6e207b85ef737c9f8 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -4,7 +4,7 @@ from nmigen import Module, Signal, Mux, Elaboratable
 
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
 
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.experiment.alu_hier import CompALUOpSubset
 
 
 from soc.experiment.alu_hier import CompALUOpSubset
 


@@ -211,14 +211,14 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 
 
 def scoreboard_sim(dut):
 
 
 def scoreboard_sim(dut):

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,

                                imm=8, imm_ok=1)
     assert result == 13
 
                                imm=8, imm_ok=1)
     assert result == 13
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)

     assert result == 65532
 
     assert result == 65532
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)

     assert result == 7
 
 
     assert result == 7
 
 

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 2bc009378ec7d350c94149a6e53d4b0e86dbcfcb..2a040917952c255ed5d5b839532b805b57018368 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -90,7 +90,7 @@ from soc.experiment.compalu_multi import go_record, CompUnitRecord
 from soc.experiment.l0_cache import PortInterface
 from soc.fu.regspec import RegSpecAPI
 
 from soc.experiment.l0_cache import PortInterface
 from soc.fu.regspec import RegSpecAPI
 

-from soc.decoder.power_enums import InternalOp, Function, LDSTMode
+from soc.decoder.power_enums import MicrOp, Function, LDSTMode

 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 from soc.decoder.power_decoder2 import Data
 
 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 from soc.decoder.power_decoder2 import Data
 


@@ -388,8 +388,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 
         # decode bits of operand (latched)
         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 
         # decode bits of operand (latched)

-        comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
-        comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
+        comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
+        comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)  # LD

         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)


@@ -550,7 +550,7 @@ def wait_for(sig, wait=True, test1st=False):
 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
                                             byterev=True):
     print ("ST", src1, src2, src3, imm, imm_ok, update)
 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
                                             byterev=True):
     print ("ST", src1, src2, src3, imm, imm_ok, update)

-    yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
+    yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)

     yield dut.oper_i.data_len.eq(2) # half-word
     yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)
     yield dut.oper_i.data_len.eq(2) # half-word
     yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)


@@ -606,7 +606,7 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
                                             byterev=True):
     print ("LD", src1, src2, imm, imm_ok, update)
 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
                                             byterev=True):
     print ("LD", src1, src2, imm, imm_ok, update)

-    yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
+    yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)

     yield dut.oper_i.data_len.eq(2) # half-word
     yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)
     yield dut.oper_i.data_len.eq(2) # half-word
     yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 6efde5933120234266721e211bfb3addd0575bc1..7c20f0e9bb328bd2b6ed1c85fb492b5b74bb5680 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -24,7 +24,7 @@ from nmigen.hdl.rec import Record, Layout
 
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
 
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 from soc.regfile.regfile import ortreereduce
 from nmutil.util import treereduce
 
 from soc.regfile.regfile import ortreereduce
 from nmutil.util import treereduce
 

diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index 83049a535826e2dca12ba029178e986f4ab6d84d..8995631fa728ae582b2b53637756dd90606bd888 100644 (file)
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -20,7 +20,7 @@ from soc.experiment.testmem import TestMemory
 
 from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
 
 
 from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
 

-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import MicrOp, Function

 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program


@@ -1178,15 +1178,15 @@ def scoreboard_sim(dut, alusim):
             instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
 
         if True:
             instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
 
         if True:

-            instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
                            0, 0, (0, 0)))

-            instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
         if False:
                            0, 0, (0, 0)))
         if False:

-            instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+            instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,

                            1, 7, (0, 0)))
         if False:
                            1, 7, (0, 0)))
         if False:

-            instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
 
         if False:
                            0, 0, (0, 0)))
 
         if False:

diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py
index 95f12dc37c2105b69a9d8b144d27664b62f0df37..2d3ba001d232e38de80c907188b86d2d63081d46 100644 (file)
--- a/src/soc/experiment/score6600_multi.py
+++ b/src/soc/experiment/score6600_multi.py
@@ -23,7 +23,7 @@ from soc.experiment.l0_cache import TstL0CacheBuffer
 from soc.experiment.alu_hier import ALU, BranchALU
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 
 from soc.experiment.alu_hier import ALU, BranchALU
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 

-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import MicrOp, Function

 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.power_decoder2 import Decode2ToExecute1Type
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.power_decoder2 import Decode2ToExecute1Type


@@ -1229,15 +1229,15 @@ def scoreboard_sim(dut, alusim):
             instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
 
         if True:
             instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
 
         if True:

-            instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
                            0, 0, (0, 0)))

-            instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
         if False:
                            0, 0, (0, 0)))
         if False:

-            instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+            instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,

                            1, 7, (0, 0)))
         if False:
                            1, 7, (0, 0)))
         if False:

-            instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+            instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,

                            0, 0, (0, 0)))
 
         if False:
                            0, 0, (0, 0)))
 
         if False:

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index 1c725b25798a56e12967a04bbbff78a5b56d968d..2c2197aaabe1390cc1cbb9486d06307c9f2b8f27 100644 (file)
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -1,4 +1,4 @@
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from random import randint, seed
 from copy import deepcopy
 
 from random import randint, seed
 from copy import deepcopy


@@ -43,9 +43,9 @@ class RegSim:
             src2 = imm
         else:
             src2 = self.regs[src2] & maxbits
             src2 = imm
         else:
             src2 = self.regs[src2] & maxbits

-        if op == InternalOp.OP_ADD:
+        if op == MicrOp.OP_ADD:

             val = src1 + src2
             val = src1 + src2

-        elif op == InternalOp.OP_MUL_L64:
+        elif op == MicrOp.OP_MUL_L64:

             val = src1 * src2
             print ("mul src1, src2", src1, src2, val)
         elif op == ISUB:
             val = src1 * src2
             print ("mul src1, src2", src1, src2, val)
         elif op == ISUB:

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 31a50bba08a96791aa47b1b8281f5f8b462fca15..f32f66311a2a4398a0acb1b66eae494f58ee6940 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -14,7 +14,7 @@ from nmigen.compat.sim import run_simulation, Settle
 from nmigen.cli import rtlil
 from nmigen import Module
 
 from nmigen.cli import rtlil
 from nmigen import Module
 

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.experiment.alu_hier import ALU, DummyALU
 
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.experiment.alu_hier import ALU, DummyALU


@@ -75,37 +75,37 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 
 
 def scoreboard_sim_dummy(dut):
 
 
 def scoreboard_sim_dummy(dut):

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,

                                     imm=8, imm_ok=1)
     assert result == 5, result
 
                                     imm=8, imm_ok=1)
     assert result == 5, result
 

-    result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
+    result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,

                                     imm=8, imm_ok=1)
     assert result == 9, result
 
 
 def scoreboard_sim(dut):
                                     imm=8, imm_ok=1)
     assert result == 9, result
 
 
 def scoreboard_sim(dut):

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,

                                     imm=8, imm_ok=1)
     assert result == 13
 
                                     imm=8, imm_ok=1)
     assert result == 13
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)

     assert result == 7
 
     assert result == 7
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)

     assert result == 65532
 
     assert result == 65532
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,

                                     imm=8, imm_ok=1)
     assert result == 8
 
                                     imm=8, imm_ok=1)
     assert result == 8
 

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)

     assert result == 2
 
     # test combinatorial zero-delay operation
     # In the test ALU, any operation other than ADD, MUL or SHR
     # is zero-delay, and do a subtraction.
     assert result == 2
 
     # test combinatorial zero-delay operation
     # In the test ALU, any operation other than ADD, MUL or SHR
     # is zero-delay, and do a subtraction.

-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP)

     assert result == 3
 
 
     assert result == 3
 
 


@@ -153,7 +153,7 @@ class CompUnitParallelTest:
 
     def driver(self):
         print("Begin parallel test.")
 
     def driver(self):
         print("Begin parallel test.")

-        yield from self.operation(5, 2, InternalOp.OP_ADD)
+        yield from self.operation(5, 2, MicrOp.OP_ADD)

 
     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
                   rdmaskn=(0, 0)):
 
     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
                   rdmaskn=(0, 0)):

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 70e4a9c273a5c1718a177b470d525257b00c4d29..253714e93f083384eef0764be37c6ac16e242b12 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 
 class CompALUOpSubset(Record):
 
 
 class CompALUOpSubset(Record):


@@ -11,7 +11,7 @@ class CompALUOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data

diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index f9b7160069596ca2eb4d7dd325adab5601c21f42..0d664a750c872915ab421f58f6173088b48a0b79 100644 (file)
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 

diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index c1e71536d65546794734e336a5b77948285a9b5b..5e70d1e885b41ca50d69f57e9ee94b568d001c2e 100644 (file)
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -16,7 +16,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.main_stage import ALUMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.alu.main_stage import ALUMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -90,7 +90,7 @@ class Driver(Elaboratable):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):

-            with m.Case(InternalOp.OP_ADD):
+            with m.Case(MicrOp.OP_ADD):

 
                 # check result of 65-bit add-with-carry
                 comb += Assert(Cat(o, ca_o) == (a + b + ca_in))
 
                 # check result of 65-bit add-with-carry
                 comb += Assert(Cat(o, ca_o) == (a + b + ca_in))


@@ -105,7 +105,7 @@ class Driver(Elaboratable):
                 comb += ca_ok.eq(1)
                 comb += o_ok.eq(1)
 
                 comb += ca_ok.eq(1)
                 comb += o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_EXTS):
+            with m.Case(MicrOp.OP_EXTS):

                 for i in [1, 2, 4]:
                     with m.If(rec.data_len == i):
                         # main part, then sign-bit replicated up
                 for i in [1, 2, 4]:
                     with m.If(rec.data_len == i):
                         # main part, then sign-bit replicated up


@@ -113,12 +113,12 @@ class Driver(Elaboratable):
                         comb += Assert(o[i*8:64] == Repl(a[i*8-1], 64-(i*8)))
                 comb += o_ok.eq(1)
 
                         comb += Assert(o[i*8:64] == Repl(a[i*8-1], 64-(i*8)))
                 comb += o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_CMP):
+            with m.Case(MicrOp.OP_CMP):

                 # CMP is defined as not taking in carry
                 comb += Assume(ca_in == 0)
                 comb += Assert(o == (a+b)[0:64])
 
                 # CMP is defined as not taking in carry
                 comb += Assume(ca_in == 0)
                 comb += Assert(o == (a+b)[0:64])
 

-            with m.Case(InternalOp.OP_CMPEQB):
+            with m.Case(MicrOp.OP_CMPEQB):

                 src1 = a[0:8]
                 eqs = Signal(8)
                 for i in range(8):
                 src1 = a[0:8]
                 eqs = Signal(8)
                 for i in range(8):

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 8148d1eb0177ad2b73437066e04a03c55270af37..7dd3f3833553c75e4536b4b2ff70f94c00d45f7f 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -15,7 +15,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.output_stage import ALUOutputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.alu.output_stage import ALUOutputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -83,13 +83,13 @@ class Driver(Elaboratable):
             # sigh.  see https://bugs.libre-soc.org/show_bug.cgi?id=305#c61
             # for OP_CMP we do b-a rather than a-b (just like ADD) and
             # then invert the *test condition*.
             # sigh.  see https://bugs.libre-soc.org/show_bug.cgi?id=305#c61
             # for OP_CMP we do b-a rather than a-b (just like ADD) and
             # then invert the *test condition*.

-            with m.If(rec.insn_type == InternalOp.OP_CMP):
+            with m.If(rec.insn_type == MicrOp.OP_CMP):

                 comb += Assert(cr_out[3] == 1)
             with m.Else():
                 comb += Assert(cr_out[2] == 1)
         with m.Elif(o_signed < 0):
             # ditto as above
                 comb += Assert(cr_out[3] == 1)
             with m.Else():
                 comb += Assert(cr_out[2] == 1)
         with m.Elif(o_signed < 0):
             # ditto as above

-            with m.If(rec.insn_type == InternalOp.OP_CMP):
+            with m.If(rec.insn_type == MicrOp.OP_CMP):

                 comb += Assert(cr_out[2] == 1)
             with m.Else():
                 comb += Assert(cr_out[3] == 1)
                 comb += Assert(cr_out[2] == 1)
             with m.Else():
                 comb += Assert(cr_out[3] == 1)

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 24330676010a4cdac8081a2369a268a5372688e9..719a9a731e4c9c5f637f574fbf01203fea36df28 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -8,7 +8,7 @@ from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from nmutil.extend import exts
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 # microwatt calc_ov function.
 
 
 # microwatt calc_ov function.


@@ -46,8 +46,8 @@ class ALUMainStage(PipeModBase):
         add_a = Signal(a.width + 2, reset_less=True)
         add_b = Signal(a.width + 2, reset_less=True)
         add_o = Signal(a.width + 2, reset_less=True)
         add_a = Signal(a.width + 2, reset_less=True)
         add_b = Signal(a.width + 2, reset_less=True)
         add_o = Signal(a.width + 2, reset_less=True)

-        with m.If((op.insn_type == InternalOp.OP_ADD) |
-                  (op.insn_type == InternalOp.OP_CMP)):
+        with m.If((op.insn_type == MicrOp.OP_ADD) |
+                  (op.insn_type == MicrOp.OP_CMP)):

             # in bit 0, 1+carry_in creates carry into bit 1 and above
             comb += add_a.eq(Cat(cry_i[0], a, Const(0, 1)))
             comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1)))
             # in bit 0, 1+carry_in creates carry into bit 1 and above
             comb += add_a.eq(Cat(cry_i[0], a, Const(0, 1)))
             comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1)))


@@ -58,7 +58,7 @@ class ALUMainStage(PipeModBase):
 
         with m.Switch(op.insn_type):
             #### CMP, CMPL ####
 
         with m.Switch(op.insn_type):
             #### CMP, CMPL ####

-            with m.Case(InternalOp.OP_CMP):
+            with m.Case(MicrOp.OP_CMP):

                 # this is supposed to be inverted (b-a, not a-b)
                 # however we have a trick: instead of adding either 2x 64-bit
                 # MUXes to invert a and b, or messing with a 64-bit output,
                 # this is supposed to be inverted (b-a, not a-b)
                 # however we have a trick: instead of adding either 2x 64-bit
                 # MUXes to invert a and b, or messing with a 64-bit output,


@@ -67,7 +67,7 @@ class ALUMainStage(PipeModBase):
                 comb += o.ok.eq(0) # use o.data but do *not* actually output
 
             #### add ####
                 comb += o.ok.eq(0) # use o.data but do *not* actually output
 
             #### add ####

-            with m.Case(InternalOp.OP_ADD):
+            with m.Case(MicrOp.OP_ADD):

                 # bit 0 is not part of the result, top bit is the carry-out
                 comb += o.data.eq(add_o[1:-1])
                 comb += o.ok.eq(1) # output register
                 # bit 0 is not part of the result, top bit is the carry-out
                 comb += o.data.eq(add_o[1:-1])
                 comb += o.ok.eq(1) # output register


@@ -87,7 +87,7 @@ class ALUMainStage(PipeModBase):
                 comb += ov_o.ok.eq(1)
 
             #### exts (sign-extend) ####
                 comb += ov_o.ok.eq(1)
 
             #### exts (sign-extend) ####

-            with m.Case(InternalOp.OP_EXTS):
+            with m.Case(MicrOp.OP_EXTS):

                 with m.If(op.data_len == 1):
                     comb += o.data.eq(exts(a, 8, 64))
                 with m.If(op.data_len == 2):
                 with m.If(op.data_len == 1):
                     comb += o.data.eq(exts(a, 8, 64))
                 with m.If(op.data_len == 2):


@@ -97,7 +97,7 @@ class ALUMainStage(PipeModBase):
                 comb += o.ok.eq(1) # output register
 
             #### cmpeqb ####
                 comb += o.ok.eq(1) # output register
 
             #### cmpeqb ####

-            with m.Case(InternalOp.OP_CMPEQB):
+            with m.Case(MicrOp.OP_CMPEQB):

                 eqs = Signal(8, reset_less=True)
                 src1 = Signal(8, reset_less=True)
                 comb += src1.eq(a[0:8])
                 eqs = Signal(8, reset_less=True)
                 src1 = Signal(8, reset_less=True)
                 comb += src1.eq(a[0:8])

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 58d9708da2ac37cc1b74ccc5faae2342ade872b3..e7d1c673c0d80685700e6f37d265bed13afbb4c7 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Cat, Repl)
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from soc.fu.common_output_stage import CommonOutputStage
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from soc.fu.common_output_stage import CommonOutputStage
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 class ALUOutputStage(CommonOutputStage):
 
 
 class ALUOutputStage(CommonOutputStage):

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 6b3ae3f3082f3460836e88990e5f55ddf3c93f39..9201c0085cd2eb5c86d864835139b72466078834 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py
index b3679e38a3ddb28075684e3743c7528da504f9d3..0bfb19344320391e7b0b76535cdf180f6ddd5598 100644 (file)
--- a/src/soc/fu/branch/br_input_record.py
+++ b/src/soc/fu/branch/br_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 
 class CompBROpSubset(Record):
 
 
 class CompBROpSubset(Record):


@@ -15,7 +15,7 @@ class CompBROpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('lk', 1),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('lk', 1),

diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py
index 0ce65226c0052e058ccf2bb8671c212b1aa985a6..52409c4ea6617c59df754481381f6c23a28d0137 100644 (file)
--- a/src/soc/fu/branch/formal/proof_input_stage.py
+++ b/src/soc/fu/branch/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.branch.br_input_record import CompBROpSubset
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.branch.br_input_record import CompBROpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -57,7 +57,7 @@ class Driver(Elaboratable):
             comb += Assert(dut.o.a == a)
 
         with m.If(rec.imm_data.imm_ok &
             comb += Assert(dut.o.a == a)
 
         with m.If(rec.imm_data.imm_ok &

-                  ~(rec.insn_type == InternalOp.OP_RLC)):
+                  ~(rec.insn_type == MicrOp.OP_RLC)):

             comb += Assert(dut.o.b == rec.imm_data.imm)
         with m.Else():
             comb += Assert(dut.o.b == b)
             comb += Assert(dut.o.b == rec.imm_data.imm)
         with m.Else():
             comb += Assert(dut.o.b == b)

diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py
index 394c43469d62d72c70d99c8185381e6bc9f35deb..3e1879aef10213831bebd6573343f801079d1de3 100644 (file)
--- a/src/soc/fu/branch/formal/proof_main_stage.py
+++ b/src/soc/fu/branch/formal/proof_main_stage.py
@@ -16,7 +16,7 @@ from nmigen.cli import rtlil
 from soc.fu.branch.main_stage import BranchMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.branch.main_stage import BranchMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -101,7 +101,7 @@ class Driver(Elaboratable):
         with m.Switch(rec.insn_type):
 
             #### b ####
         with m.Switch(rec.insn_type):
 
             #### b ####

-            with m.Case(InternalOp.OP_B):
+            with m.Case(MicrOp.OP_B):

                 # Extract target address
                 LI = i_fields.LI[0:-1]
                 imm = exts(LI, LI.shape().width, 64-2) * 4
                 # Extract target address
                 LI = i_fields.LI[0:-1]
                 imm = exts(LI, LI.shape().width, 64-2) * 4


@@ -126,7 +126,7 @@ class Driver(Elaboratable):
                 comb += Assert(dut.o.ctr.ok == 0)
 
             #### bc ####
                 comb += Assert(dut.o.ctr.ok == 0)
 
             #### bc ####

-            with m.Case(InternalOp.OP_BC):
+            with m.Case(MicrOp.OP_BC):

                 # Assert that branches are conditional
                 comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
 
                 # Assert that branches are conditional
                 comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
 


@@ -151,7 +151,7 @@ class Driver(Elaboratable):
                 with m.Else():
                     comb += Assert(dut.o.ctr.ok == 0)
             #### bctar/bcctr/bclr ####
                 with m.Else():
                     comb += Assert(dut.o.ctr.ok == 0)
             #### bctar/bcctr/bclr ####

-            with m.Case(InternalOp.OP_BCREG):
+            with m.Case(MicrOp.OP_BCREG):

                 # assert that the condition is good
                 comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
 
                 # assert that the condition is good
                 comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
 

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 9d7c2a543d8eeb85480679bef826fd4f3c1f3397..a46a95c3684116af70859976976bdacf63ca5543 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -13,7 +13,7 @@ from nmigen import (Module, Signal, Cat, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -70,7 +70,7 @@ class BranchMainStage(PipeModBase):
         br_taken = Signal(reset_less=True)
 
         # Handle absolute or relative branches
         br_taken = Signal(reset_less=True)
 
         # Handle absolute or relative branches

-        with m.If(AA | (op.insn_type == InternalOp.OP_BCREG)):
+        with m.If(AA | (op.insn_type == MicrOp.OP_BCREG)):

             comb += br_addr.eq(br_imm_addr)
         with m.Else():
             comb += br_addr.eq(br_imm_addr + cia)
             comb += br_addr.eq(br_imm_addr)
         with m.Else():
             comb += br_addr.eq(br_imm_addr + cia)


@@ -121,18 +121,18 @@ class BranchMainStage(PipeModBase):
         ### Main Switch Statement ###
         with m.Switch(op.insn_type):
             #### branch ####
         ### Main Switch Statement ###
         with m.Switch(op.insn_type):
             #### branch ####

-            with m.Case(InternalOp.OP_B):
+            with m.Case(MicrOp.OP_B):

                 LI = i_fields.LI[0:-1]
                 comb += br_imm_addr.eq(br_ext(LI))
                 comb += br_taken.eq(1)
             #### branch conditional ####
                 LI = i_fields.LI[0:-1]
                 comb += br_imm_addr.eq(br_ext(LI))
                 comb += br_taken.eq(1)
             #### branch conditional ####

-            with m.Case(InternalOp.OP_BC):
+            with m.Case(MicrOp.OP_BC):

                 BD = b_fields.BD[0:-1]
                 comb += br_imm_addr.eq(br_ext(BD))
                 comb += br_taken.eq(bc_taken)
                 comb += ctr_o.ok.eq(ctr_write)
             #### branch conditional reg ####
                 BD = b_fields.BD[0:-1]
                 comb += br_imm_addr.eq(br_ext(BD))
                 comb += br_taken.eq(bc_taken)
                 comb += ctr_o.ok.eq(ctr_write)
             #### branch conditional reg ####

-            with m.Case(InternalOp.OP_BCREG):
+            with m.Case(MicrOp.OP_BCREG):

                 xo = self.fields.FormXL.XO[0:-1]
                 with m.If(xo[9] & ~xo[5]):
                     comb += br_imm_addr.eq(Cat(Const(0, 2), fast1[2:]))
                 xo = self.fields.FormXL.XO[0:-1]
                 with m.If(xo[9] & ~xo[5]):
                     comb += br_imm_addr.eq(Cat(Const(0, 2), fast1[2:]))

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 947cff28d5292a0f94b8d8b75b9c9147bca41a38..70796198d75fcaedd8c450ab186279eca371a3f3 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index d5916a0a7a0aa803f5f0a3a39b93a4d4d1b86b10..4dbb5c0712a59ac3451061071d6f907037aa69fb 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -3,7 +3,7 @@
 # generation for subtraction, should happen here
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
 # generation for subtraction, should happen here
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 from soc.decoder.power_enums import CryIn
 
 
 from soc.decoder.power_enums import CryIn
 
 

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 4a9f391d5cfff47487b4d6b925f3effef7ce2749..cc0f00a38063df1ee54b3dfdd2c1cbf758b3bf3a 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -3,7 +3,7 @@
 from nmigen import (Module, Signal, Cat, Const)
 from nmutil.pipemodbase import PipeModBase
 from ieee754.part.partsig import PartitionedSignal
 from nmigen import (Module, Signal, Cat, Const)
 from nmutil.pipemodbase import PipeModBase
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 class CommonOutputStage(PipeModBase):
 
 
 class CommonOutputStage(PipeModBase):


@@ -60,8 +60,8 @@ class CommonOutputStage(PipeModBase):
         # that can be used as a test of whether to invert the +ve/-ve test
         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
 
         # that can be used as a test of whether to invert the +ve/-ve test
         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
 

-        comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
-        comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
+        comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
+        comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)

         # nope - if *processor* mode is 32-bit
         #with m.If(op.is_32bit):
         #    comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
         # nope - if *processor* mode is 32-bit
         #with m.If(op.is_32bit):
         #    comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB

diff --git a/src/soc/fu/compunits/formal/test_compunit.py b/src/soc/fu/compunits/formal/test_compunit.py
index 956b5d7730cde0ae75ba7a267d3d53c1c9a571ae..153879baa65117a412ee2c364d2ddf88b357310a 100644 (file)
--- a/src/soc/fu/compunits/formal/test_compunit.py
+++ b/src/soc/fu/compunits/formal/test_compunit.py
@@ -6,7 +6,7 @@ from soc.fu.compunits.compunits import FunctionUnitBaseSingle
 from soc.experiment.alu_hier import DummyALU
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.experiment.alu_hier import DummyALU
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 class MaskGenTestCase(FHDLTestCase):
 import unittest
 
 class MaskGenTestCase(FHDLTestCase):


@@ -22,7 +22,7 @@ class MaskGenTestCase(FHDLTestCase):
             yield dut.src1_i.eq(0x5)
             yield dut.src2_i.eq(0x5)
             yield dut.issue_i.eq(1)
             yield dut.src1_i.eq(0x5)
             yield dut.src2_i.eq(0x5)
             yield dut.issue_i.eq(1)

-            yield dut.oper_i.insn_type.eq(InternalOp.OP_ADD)
+            yield dut.oper_i.insn_type.eq(MicrOp.OP_ADD)

             yield
             yield dut.issue_i.eq(0)
             yield
             yield
             yield dut.issue_i.eq(0)
             yield

diff --git a/src/soc/fu/cr/cr_input_record.py b/src/soc/fu/cr/cr_input_record.py
index 11e85d1568bcdf666b6ce93f59e501a0fbea4804..bfe4ab82e2ce3e970a53a6324bb07ca3e4ab40b0 100644 (file)
--- a/src/soc/fu/cr/cr_input_record.py
+++ b/src/soc/fu/cr/cr_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)

 
 
 class CompCROpSubset(Record):
 
 
 class CompCROpSubset(Record):


@@ -11,7 +11,7 @@ class CompCROpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('insn', 32),
                   ('read_cr_whole', 1),
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('read_cr_whole', 1),

diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py
index 96dbe4bf5c344e7138c9ec602597e545d97d3001..c24fb42cd111f9d517ccc2e5f46270dbf32d8f9b 100644 (file)
--- a/src/soc/fu/cr/formal/proof_main_stage.py
+++ b/src/soc/fu/cr/formal/proof_main_stage.py
@@ -14,7 +14,7 @@ from nmigen.cli import rtlil
 from soc.fu.cr.main_stage import CRMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.cr.main_stage import CRMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -76,7 +76,7 @@ class Driver(Elaboratable):
 
         with m.Switch(rec.insn_type):
             # CR_ISEL takes cr_a
 
         with m.Switch(rec.insn_type):
             # CR_ISEL takes cr_a

-            with m.Case(InternalOp.OP_ISEL):
+            with m.Case(MicrOp.OP_ISEL):

                 # grab the MSBs of the cr bit selector
                 bc = Signal(3, reset_less=True)
                 comb += bc.eq(a_fields.BC[2:5])
                 # grab the MSBs of the cr bit selector
                 bc = Signal(3, reset_less=True)
                 comb += bc.eq(a_fields.BC[2:5])


@@ -88,7 +88,7 @@ class Driver(Elaboratable):
 
             # For OP_CROP, we need to input the corresponding CR
             # registers for BA, BB, and BT
 
             # For OP_CROP, we need to input the corresponding CR
             # registers for BA, BB, and BT

-            with m.Case(InternalOp.OP_CROP):
+            with m.Case(MicrOp.OP_CROP):

                 # grab the MSBs of the 3 bit selectors
                 bt = Signal(3, reset_less=True)
                 ba = Signal(3, reset_less=True)
                 # grab the MSBs of the 3 bit selectors
                 bt = Signal(3, reset_less=True)
                 ba = Signal(3, reset_less=True)


@@ -111,7 +111,7 @@ class Driver(Elaboratable):
                     with m.Else():
                         comb += cr_output_arr[i].eq(dut.o.cr.data)
 
                     with m.Else():
                         comb += cr_output_arr[i].eq(dut.o.cr.data)
 

-            with m.Case(InternalOp.OP_MCRF):
+            with m.Case(MicrOp.OP_MCRF):

                 # This does a similar thing to OP_CROP above, with
                 # less inputs. The CR selection fields are already 3
                 # bits so there's no need to grab only the MSBs
                 # This does a similar thing to OP_CROP above, with
                 # less inputs. The CR selection fields are already 3
                 # bits so there's no need to grab only the MSBs


@@ -128,7 +128,7 @@ class Driver(Elaboratable):
                         comb += cr_output_arr[i].eq(dut.o.cr.data)
 
             # Set the input similar to OP_MCRF
                         comb += cr_output_arr[i].eq(dut.o.cr.data)
 
             # Set the input similar to OP_MCRF

-            with m.Case(InternalOp.OP_SETB):
+            with m.Case(MicrOp.OP_SETB):

                 comb += dut.i.cr_a.eq(cr_input_arr[bfa])
 
             # For the other two, they take the full CR as input, and
                 comb += dut.i.cr_a.eq(cr_input_arr[bfa])
 
             # For the other two, they take the full CR as input, and


@@ -159,13 +159,13 @@ class Driver(Elaboratable):
 
         FXM = xfx_fields.FXM[0:-1]
         with m.Switch(rec.insn_type):
 
         FXM = xfx_fields.FXM[0:-1]
         with m.Switch(rec.insn_type):

-            with m.Case(InternalOp.OP_MTCRF):
+            with m.Case(MicrOp.OP_MTCRF):

                 for i in range(8):
                     with m.If(FXM[i]):
                         comb += Assert(cr_o[4*i:4*i+4] == a[4*i:4*i+4])
                 comb += full_cr_o_ok.eq(1)
 
                 for i in range(8):
                     with m.If(FXM[i]):
                         comb += Assert(cr_o[4*i:4*i+4] == a[4*i:4*i+4])
                 comb += full_cr_o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_MFCR):
+            with m.Case(MicrOp.OP_MFCR):

                 with m.If(rec.insn[20]):  # mfocrf
                     for i in range(8):
                         with m.If(FXM[i]):
                 with m.If(rec.insn[20]):  # mfocrf
                     for i in range(8):
                         with m.If(FXM[i]):


@@ -176,7 +176,7 @@ class Driver(Elaboratable):
                     comb += Assert(o == cr)
                 comb += o_ok.eq(1)
 
                     comb += Assert(o == cr)
                 comb += o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_MCRF):
+            with m.Case(MicrOp.OP_MCRF):

                 BF = xl_fields.BF[0:-1]
                 BFA = xl_fields.BFA[0:-1]
                 for i in range(4):
                 BF = xl_fields.BF[0:-1]
                 BFA = xl_fields.BFA[0:-1]
                 for i in range(4):


@@ -186,7 +186,7 @@ class Driver(Elaboratable):
                         comb += Assert(cr_o[i*4:i*4+4] == cr[i*4:i*4+4])
                 comb += cr_o_ok.eq(1)
 
                         comb += Assert(cr_o[i*4:i*4+4] == cr[i*4:i*4+4])
                 comb += cr_o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_CROP):
+            with m.Case(MicrOp.OP_CROP):

                 bt = Signal(xl_fields.BT[0:-1].shape(), reset_less=True)
                 ba = Signal(xl_fields.BA[0:-1].shape(), reset_less=True)
                 bb = Signal(xl_fields.BB[0:-1].shape(), reset_less=True)
                 bt = Signal(xl_fields.BT[0:-1].shape(), reset_less=True)
                 ba = Signal(xl_fields.BA[0:-1].shape(), reset_less=True)
                 bb = Signal(xl_fields.BB[0:-1].shape(), reset_less=True)


@@ -222,7 +222,7 @@ class Driver(Elaboratable):
 
                 comb += cr_o_ok.eq(1)
 
 
                 comb += cr_o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_ISEL):
+            with m.Case(MicrOp.OP_ISEL):

                 # Extract the bit selector of the CR
                 bc = Signal(a_fields.BC[0:-1].shape(), reset_less=True)
                 comb += bc.eq(a_fields.BC[0:-1])
                 # Extract the bit selector of the CR
                 bc = Signal(a_fields.BC[0:-1].shape(), reset_less=True)
                 comb += bc.eq(a_fields.BC[0:-1])


@@ -235,7 +235,7 @@ class Driver(Elaboratable):
                 comb += Assert(o == Mux(cr_bit, a, b))
                 comb += o_ok.eq(1)
 
                 comb += Assert(o == Mux(cr_bit, a, b))
                 comb += o_ok.eq(1)
 

-            with m.Case(InternalOp.OP_SETB):
+            with m.Case(MicrOp.OP_SETB):

                 with m.If(cr_arr[4*bfa]):
                     comb += Assert(o == ((1<<64)-1))
                 with m.Elif(cr_arr[4*bfa+1]):
                 with m.If(cr_arr[4*bfa]):
                     comb += Assert(o == ((1<<64)-1))
                 with m.Elif(cr_arr[4*bfa+1]):

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 14828577495e1a1d76cb2097ddb83ec7825f4469..27aa667042c2891d3f3de8e43290cdb2d332c53a 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -12,7 +12,7 @@
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.cr.pipe_data import CRInputData, CROutputData
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.cr.pipe_data import CRInputData, CROutputData

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -54,7 +54,7 @@ class CRMainStage(PipeModBase):
 
         with m.Switch(op.insn_type):
             ##### mcrf #####
 
         with m.Switch(op.insn_type):
             ##### mcrf #####

-            with m.Case(InternalOp.OP_MCRF):
+            with m.Case(MicrOp.OP_MCRF):

                 # MCRF copies the 4 bits of crA to crB (for instance
                 # copying cr2 to cr1)
                 # Since it takes in a 4 bit cr, and outputs a 4 bit
                 # MCRF copies the 4 bits of crA to crB (for instance
                 # copying cr2 to cr1)
                 # Since it takes in a 4 bit cr, and outputs a 4 bit


@@ -63,7 +63,7 @@ class CRMainStage(PipeModBase):
                 comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### crand, cror, crnor etc. #####
                 comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### crand, cror, crnor etc. #####

-            with m.Case(InternalOp.OP_CROP):
+            with m.Case(MicrOp.OP_CROP):

                 # crand/cror and friends get decoded to the same opcode, but
                 # one of the fields inside the instruction is a 4 bit lookup
                 # table. This lookup table gets indexed by bits a and b from
                 # crand/cror and friends get decoded to the same opcode, but
                 # one of the fields inside the instruction is a 4 bit lookup
                 # table. This lookup table gets indexed by bits a and b from


@@ -109,7 +109,7 @@ class CRMainStage(PipeModBase):
                 comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             ##### mtcrf #####
                 comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             ##### mtcrf #####

-            with m.Case(InternalOp.OP_MTCRF):
+            with m.Case(MicrOp.OP_MTCRF):

                 # mtocrf and mtcrf are essentially identical
                 # put input (RA) - mask-selected - into output CR, leave
                 # rest of CR alone.
                 # mtocrf and mtcrf are essentially identical
                 # put input (RA) - mask-selected - into output CR, leave
                 # rest of CR alone.


@@ -117,7 +117,7 @@ class CRMainStage(PipeModBase):
                 comb += full_cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### mfcr #####
                 comb += full_cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### mfcr #####

-            with m.Case(InternalOp.OP_MFCR):
+            with m.Case(MicrOp.OP_MFCR):

                 # Ugh. mtocrf and mtcrf have one random bit differentiating
                 # them. This bit is not in any particular field, so this
                 # extracts that bit from the instruction
                 # Ugh. mtocrf and mtcrf have one random bit differentiating
                 # them. This bit is not in any particular field, so this
                 # extracts that bit from the instruction


@@ -135,7 +135,7 @@ class CRMainStage(PipeModBase):
                 comb += rt_o.ok.eq(1) # indicate "INT reg changed"
 
             # ##### isel #####
                 comb += rt_o.ok.eq(1) # indicate "INT reg changed"
 
             # ##### isel #####

-            with m.Case(InternalOp.OP_ISEL):
+            with m.Case(MicrOp.OP_ISEL):

                 # just like in branch, CR0-7 is incoming into cr_a, we
                 # need to select from the last 2 bits of BC
                 a_fields = self.fields.FormA
                 # just like in branch, CR0-7 is incoming into cr_a, we
                 # need to select from the last 2 bits of BC
                 a_fields = self.fields.FormA


@@ -150,7 +150,7 @@ class CRMainStage(PipeModBase):
                 comb += rt_o.eq(Mux(cr_bit, a, b))
                 comb += rt_o.ok.eq(1) # indicate "INT reg changed"
 
                 comb += rt_o.eq(Mux(cr_bit, a, b))
                 comb += rt_o.ok.eq(1) # indicate "INT reg changed"
 

-            with m.Case(InternalOp.OP_SETB):
+            with m.Case(MicrOp.OP_SETB):

                 with m.If(cr_a[3]):
                     comb += rt_o.data.eq(-1)
                 with m.Elif(cr_a[2]):
                 with m.If(cr_a[3]):
                     comb += rt_o.data.eq(-1)
                 with m.Elif(cr_a[2]):

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index 32f29e688400efbc298d41f6bc15b88ba51e5251..aa53845abc6941f03631502d45bf9cd38a43d63c 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -4,7 +4,7 @@
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from ieee754.part.partsig import PartitionedSignal
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange

diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py
index f3baa1b67257fe34b770822581829d87cda6a4bb..469127dddf4bfcee01444e3c87a591ee70bb0a96 100644 (file)
--- a/src/soc/fu/div/formal/proof_main_stage.py
+++ b/src/soc/fu/div/formal/proof_main_stage.py
@@ -16,7 +16,7 @@ from nmigen.cli import rtlil
 from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -78,14 +78,14 @@ class Driver(Elaboratable):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):

-            with m.Case(InternalOp.OP_AND):
+            with m.Case(MicrOp.OP_AND):

                 comb += Assert(dut.o.o == a & b)
                 comb += Assert(dut.o.o == a & b)

-            with m.Case(InternalOp.OP_OR):
+            with m.Case(MicrOp.OP_OR):

                 comb += Assert(dut.o.o == a | b)
                 comb += Assert(dut.o.o == a | b)

-            with m.Case(InternalOp.OP_XOR):
+            with m.Case(MicrOp.OP_XOR):

                 comb += Assert(dut.o.o == a ^ b)
 
                 comb += Assert(dut.o.o == a ^ b)
 

-            with m.Case(InternalOp.OP_POPCNT):
+            with m.Case(MicrOp.OP_POPCNT):

                 with m.If(rec.data_len == 8):
                     comb += Assert(dut.o.o == self.popcount(a, 64))
                 with m.If(rec.data_len == 4):
                 with m.If(rec.data_len == 8):
                     comb += Assert(dut.o.o == self.popcount(a, 64))
                 with m.If(rec.data_len == 4):


@@ -98,7 +98,7 @@ class Driver(Elaboratable):
                         comb += Assert(dut.o.o[i*8:(i+1)*8] ==
                                        self.popcount(a[i*8:(i+1)*8], 8))
 
                         comb += Assert(dut.o.o[i*8:(i+1)*8] ==
                                        self.popcount(a[i*8:(i+1)*8], 8))
 

-            with m.Case(InternalOp.OP_PRTY):
+            with m.Case(MicrOp.OP_PRTY):

                 with m.If(rec.data_len == 8):
                     result = 0
                     for i in range(8):
                 with m.If(rec.data_len == 8):
                     result = 0
                     for i in range(8):


@@ -112,7 +112,7 @@ class Driver(Elaboratable):
                         result_high = result_high ^ a[i*8 + 32]
                     comb += Assert(dut.o.o[0:32] == result_low)
                     comb += Assert(dut.o.o[32:64] == result_high)
                         result_high = result_high ^ a[i*8 + 32]
                     comb += Assert(dut.o.o[0:32] == result_low)
                     comb += Assert(dut.o.o[32:64] == result_high)

-            with m.Case(InternalOp.OP_CNTZ):
+            with m.Case(MicrOp.OP_CNTZ):

                 XO = dut.fields.FormX.XO[0:-1]
                 with m.If(rec.is_32bit):
                     m.submodules.pe32 = pe32 = PriorityEncoder(32)
                 XO = dut.fields.FormX.XO[0:-1]
                 with m.If(rec.is_32bit):
                     m.submodules.pe32 = pe32 = PriorityEncoder(32)

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index b5b286a695475c06b8700bdbff8dd611b02c47f8..5da7f6c7244aeb4980e429875ae01fa35a508002 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -9,7 +9,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.div.pipe_data import DivMulOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.div.pipe_data import DivMulOutputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -115,7 +115,7 @@ class DivOutputStage(PipeModBase):
 
         with m.If(~ov): # result is valid (no overflow)
             with m.Switch(op.insn_type):
 
         with m.If(~ov): # result is valid (no overflow)
             with m.Switch(op.insn_type):

-                with m.Case(InternalOp.OP_DIVE):
+                with m.Case(MicrOp.OP_DIVE):

                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divweo behavior
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divweo behavior


@@ -124,7 +124,7 @@ class DivOutputStage(PipeModBase):
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)

-                with m.Case(InternalOp.OP_DIV):
+                with m.Case(MicrOp.OP_DIV):

                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divwo behavior
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divwo behavior


@@ -133,7 +133,7 @@ class DivOutputStage(PipeModBase):
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)

-                with m.Case(InternalOp.OP_MOD):
+                with m.Case(MicrOp.OP_MOD):

                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's modsw behavior
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's modsw behavior

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 25daa201b8dc1e0b1dd80413b87d77683a47e3f8..11619fc7d22c78f5a218e9bb8468a0b6d47ad5e5 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DIVInputData
 from ieee754.part.partsig import PartitionedSignal
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DIVInputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -54,10 +54,10 @@ class DivSetupStage(PipeModBase):
 
         # check for absolute overflow condition (32/64)
         comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)
 
         # check for absolute overflow condition (32/64)
         comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)

-                                        & (op.insn_type == InternalOp.OP_DIVE))
+                                        & (op.insn_type == MicrOp.OP_DIVE))

 
         comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])
 
         comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])

-                                        & (op.insn_type == InternalOp.OP_DIVE))
+                                        & (op.insn_type == MicrOp.OP_DIVE))

 
         # set divisor based on 32/64 bit mode (must be absolute)
         comb += eq32(op.is_32bit, divisor_o, abs_dor)
 
         # set divisor based on 32/64 bit mode (must be absolute)
         comb += eq32(op.is_32bit, divisor_o, abs_dor)


@@ -70,10 +70,10 @@ class DivSetupStage(PipeModBase):
 
         with m.Switch(op.insn_type):
             # div/mod takes straight (absolute) dividend
 
         with m.Switch(op.insn_type):
             # div/mod takes straight (absolute) dividend

-            with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD):
+            with m.Case(MicrOp.OP_DIV, MicrOp.OP_MOD):

                 comb += eq32(op.is_32bit, dividend_o, abs_dend)
             # extended div shifts dividend up
                 comb += eq32(op.is_32bit, dividend_o, abs_dend)
             # extended div shifts dividend up

-            with m.Case(InternalOp.OP_DIVE):
+            with m.Case(MicrOp.OP_DIVE):

                 with m.If(op.is_32bit):
                     comb += dividend_o.eq(abs_dend[0:32] << 32)
                 with m.Else():
                 with m.If(op.is_32bit):
                     comb += dividend_o.eq(abs_dend[0:32] << 32)
                 with m.Else():

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 65aa0801e0b17157092dcda32e84c54821b676b3..204e43154626ec08988537cefb78519a0edb6037 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py
index 2abf6c22313b209fad2c060837c86b686fe11d92..03851d43207791290804d14e984fee37fca33169 100644 (file)
--- a/src/soc/fu/ldst/ldst_input_record.py
+++ b/src/soc/fu/ldst/ldst_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, LDSTMode
+from soc.decoder.power_enums import MicrOp, Function, LDSTMode

 
 
 class CompLDSTOpSubset(Record):
 
 
 class CompLDSTOpSubset(Record):


@@ -13,7 +13,7 @@ class CompLDSTOpSubset(Record):
     note: rc / oe is needed (later) for st*cx when it comes to setting OV/SO
     """
     def __init__(self, name=None):
     note: rc / oe is needed (later) for st*cx when it comes to setting OV/SO
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('zero_a', 1),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('zero_a', 1),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later

diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 6336f0ae61141f7a6f8a5dd1554dd0b37be3ddef..9e601e3e4039dd02231b1b67d319ec76985d8cd0 100644 (file)
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index 16f3df0432413d6eb963db6d945c88eb537368d2..ab6e392e75061862365c331d05acecb84d7b5406 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -57,7 +57,7 @@ class Driver(Elaboratable):
             comb += Assert(dut.o.a == a)
 
         with m.If(rec.imm_data.imm_ok &
             comb += Assert(dut.o.a == a)
 
         with m.If(rec.imm_data.imm_ok &

-                  ~(rec.insn_type == InternalOp.OP_RLC)):
+                  ~(rec.insn_type == MicrOp.OP_RLC)):

             comb += Assert(dut.o.b == rec.imm_data.imm)
         with m.Else():
             comb += Assert(dut.o.b == b)
             comb += Assert(dut.o.b == rec.imm_data.imm)
         with m.Else():
             comb += Assert(dut.o.b == b)

diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py
index de1c788d4fbf482a15b72ce86053ca56ee8b828b..e7cf254a8f31be2a2a783b47027261a7a9116ae1 100644 (file)
--- a/src/soc/fu/logical/formal/proof_main_stage.py
+++ b/src/soc/fu/logical/formal/proof_main_stage.py
@@ -16,7 +16,7 @@ from nmigen.cli import rtlil
 from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -82,14 +82,14 @@ class Driver(Elaboratable):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):

-            with m.Case(InternalOp.OP_AND):
+            with m.Case(MicrOp.OP_AND):

                 comb += Assert(o == a & b)
                 comb += Assert(o == a & b)

-            with m.Case(InternalOp.OP_OR):
+            with m.Case(MicrOp.OP_OR):

                 comb += Assert(o == a | b)
                 comb += Assert(o == a | b)

-            with m.Case(InternalOp.OP_XOR):
+            with m.Case(MicrOp.OP_XOR):

                 comb += Assert(o == a ^ b)
 
                 comb += Assert(o == a ^ b)
 

-            with m.Case(InternalOp.OP_POPCNT):
+            with m.Case(MicrOp.OP_POPCNT):

                 with m.If(rec.data_len == 8):
                     comb += Assert(o == simple_popcount(a, 64))
                 with m.If(rec.data_len == 4):
                 with m.If(rec.data_len == 8):
                     comb += Assert(o == simple_popcount(a, 64))
                 with m.If(rec.data_len == 4):


@@ -101,7 +101,7 @@ class Driver(Elaboratable):
                         slc = slice(i*8, (i+1)*8)
                         comb += Assert(o[slc] == simple_popcount(a[slc], 8))
 
                         slc = slice(i*8, (i+1)*8)
                         comb += Assert(o[slc] == simple_popcount(a[slc], 8))
 

-            with m.Case(InternalOp.OP_PRTY):
+            with m.Case(MicrOp.OP_PRTY):

                 with m.If(rec.data_len == 8):
                     result = 0
                     for i in range(8):
                 with m.If(rec.data_len == 8):
                     result = 0
                     for i in range(8):


@@ -116,7 +116,7 @@ class Driver(Elaboratable):
                     comb += Assert(o[0:32] == result_low)
                     comb += Assert(o[32:64] == result_high)
 
                     comb += Assert(o[0:32] == result_low)
                     comb += Assert(o[32:64] == result_high)
 

-            with m.Case(InternalOp.OP_CNTZ):
+            with m.Case(MicrOp.OP_CNTZ):

                 XO = dut.fields.FormX.XO[0:-1]
                 with m.If(rec.is_32bit):
                     m.submodules.pe32 = pe32 = PriorityEncoder(32)
                 XO = dut.fields.FormX.XO[0:-1]
                 with m.If(rec.is_32bit):
                     m.submodules.pe32 = pe32 = PriorityEncoder(32)


@@ -145,7 +145,7 @@ class Driver(Elaboratable):
                         comb += pe64.i.eq(a[0:64][::-1])
                         comb += Assert(o == peo64)
 
                         comb += pe64.i.eq(a[0:64][::-1])
                         comb += Assert(o == peo64)
 

-            with m.Case(InternalOp.OP_CMPB):
+            with m.Case(MicrOp.OP_CMPB):

                 for i in range(8):
                     slc = slice(i*8, (i+1)*8)
                     with m.If(a[slc] == b[slc]):
                 for i in range(8):
                     slc = slice(i*8, (i+1)*8)
                     with m.If(a[slc] == b[slc]):


@@ -153,7 +153,7 @@ class Driver(Elaboratable):
                     with m.Else():
                         comb += Assert(o[slc] == 0)
 
                     with m.Else():
                         comb += Assert(o[slc] == 0)
 

-            with m.Case(InternalOp.OP_BPERM):
+            with m.Case(MicrOp.OP_BPERM):

                 # note that this is a copy of the beautifully-documented
                 # proof_bpermd.py
                 comb += Assert(o[8:] == 0)
                 # note that this is a copy of the beautifully-documented
                 # proof_bpermd.py
                 comb += Assert(o[8:] == 0)

diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py
index 92de6388e0ff7f8f17ed736f69adb64083e8b31f..7040f0e56ad47cc9d09e83fb71b2144e50908152 100644 (file)
--- a/src/soc/fu/logical/logical_input_record.py
+++ b/src/soc/fu/logical/logical_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 
 class CompLogicalOpSubset(Record):
 
 
 class CompLogicalOpSubset(Record):


@@ -11,7 +11,7 @@ class CompLogicalOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index 1815431a839bbaa941abd7767ebc263c18d1c267..925455b3ad000356fc1a283b3c2e800122348c1a 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -13,7 +13,7 @@ from soc.fu.logical.bpermd import Bpermd
 from soc.fu.logical.popcount import Popcount
 from soc.fu.logical.pipe_data import LogicalOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.logical.popcount import Popcount
 from soc.fu.logical.pipe_data import LogicalOutputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -47,15 +47,15 @@ class LogicalMainStage(PipeModBase):
         with m.Switch(op.insn_type):
 
             ###### AND, OR, XOR #######
         with m.Switch(op.insn_type):
 
             ###### AND, OR, XOR #######

-            with m.Case(InternalOp.OP_AND):
+            with m.Case(MicrOp.OP_AND):

                 comb += o.data.eq(a & b)
                 comb += o.data.eq(a & b)

-            with m.Case(InternalOp.OP_OR):
+            with m.Case(MicrOp.OP_OR):

                 comb += o.data.eq(a | b)
                 comb += o.data.eq(a | b)

-            with m.Case(InternalOp.OP_XOR):
+            with m.Case(MicrOp.OP_XOR):

                 comb += o.data.eq(a ^ b)
 
             ###### cmpb #######
                 comb += o.data.eq(a ^ b)
 
             ###### cmpb #######

-            with m.Case(InternalOp.OP_CMPB):
+            with m.Case(MicrOp.OP_CMPB):

                 l = []
                 for i in range(8):
                     slc = slice(i*8, (i+1)*8)
                 l = []
                 for i in range(8):
                     slc = slice(i*8, (i+1)*8)


@@ -63,14 +63,14 @@ class LogicalMainStage(PipeModBase):
                 comb += o.data.eq(Cat(*l))
 
             ###### popcount #######
                 comb += o.data.eq(Cat(*l))
 
             ###### popcount #######

-            with m.Case(InternalOp.OP_POPCNT):
+            with m.Case(MicrOp.OP_POPCNT):

                 comb += popcount.a.eq(a)
                 comb += popcount.b.eq(b)
                 comb += popcount.data_len.eq(op.data_len)
                 comb += o.data.eq(popcount.o)
 
             ###### parity #######
                 comb += popcount.a.eq(a)
                 comb += popcount.b.eq(b)
                 comb += popcount.data_len.eq(op.data_len)
                 comb += o.data.eq(popcount.o)
 
             ###### parity #######

-            with m.Case(InternalOp.OP_PRTY):
+            with m.Case(MicrOp.OP_PRTY):

                 # strange instruction which XORs together the LSBs of each byte
                 par0 = Signal(reset_less=True)
                 par1 = Signal(reset_less=True)
                 # strange instruction which XORs together the LSBs of each byte
                 par0 = Signal(reset_less=True)
                 par1 = Signal(reset_less=True)


@@ -83,7 +83,7 @@ class LogicalMainStage(PipeModBase):
                     comb += o[32].eq(par1)
 
             ###### cntlz #######
                     comb += o[32].eq(par1)
 
             ###### cntlz #######

-            with m.Case(InternalOp.OP_CNTZ):
+            with m.Case(MicrOp.OP_CNTZ):

                 XO = self.fields.FormX.XO[0:-1]
                 count_right = Signal(reset_less=True)
                 comb += count_right.eq(XO[-1])
                 XO = self.fields.FormX.XO[0:-1]
                 count_right = Signal(reset_less=True)
                 comb += count_right.eq(XO[-1])


@@ -102,7 +102,7 @@ class LogicalMainStage(PipeModBase):
                 comb += o.data.eq(Mux(op.is_32bit, clz.lz-32, clz.lz))
 
             ###### bpermd #######
                 comb += o.data.eq(Mux(op.is_32bit, clz.lz-32, clz.lz))
 
             ###### bpermd #######

-            with m.Case(InternalOp.OP_BPERM):
+            with m.Case(MicrOp.OP_BPERM):

                 comb += bpermd.rs.eq(a)
                 comb += bpermd.rb.eq(b)
                 comb += o.data.eq(bpermd.ra)
                 comb += bpermd.rs.eq(a)
                 comb += bpermd.rb.eq(b)
                 comb += o.data.eq(bpermd.ra)

diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py
index 7f833b3edeebe23326e6827a8b10be5effb67d7d..a985511f75823b6bc7ac374a0299693ca91b9efd 100644 (file)
--- a/src/soc/fu/logical/output_stage.py
+++ b/src/soc/fu/logical/output_stage.py
@@ -6,7 +6,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.common_output_stage import CommonOutputStage
 from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.common_output_stage import CommonOutputStage
 from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 class LogicalOutputStage(CommonOutputStage):
 
 
 class LogicalOutputStage(CommonOutputStage):

diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py
index 0e44e5e8ecf732f670904ff79fac5ce2987dde3e..890475a6668a3191bfd70889c02001a9cc0ef4ac 100644 (file)
--- a/src/soc/fu/mul/formal/proof_main_stage.py
+++ b/src/soc/fu/mul/formal/proof_main_stage.py
@@ -10,7 +10,7 @@ from nmigen.cli import rtlil
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -69,14 +69,14 @@ class Driver(Elaboratable):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):

-            with m.Case(InternalOp.OP_SHL):
+            with m.Case(MicrOp.OP_SHL):

                 comb += Assume(ra == 0)
                 with m.If(rec.is_32bit):
                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
                     comb += Assert(o[32:64] == 0)
                 with m.Else():
                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
                 comb += Assume(ra == 0)
                 with m.If(rec.is_32bit):
                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
                     comb += Assert(o[32:64] == 0)
                 with m.Else():
                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))

-            with m.Case(InternalOp.OP_SHR):
+            with m.Case(MicrOp.OP_SHR):

                 comb += Assume(ra == 0)
                 with m.If(~rec.is_signed):
                     with m.If(rec.is_32bit):
                 comb += Assume(ra == 0)
                 with m.If(~rec.is_signed):
                     with m.If(rec.is_32bit):

diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py
index 51e7352ebdb2ffec8ac85e4e4148303cb0d779fb..8d85d91327fdc5f0468adb2a3ae185ce7c07e31d 100644 (file)
--- a/src/soc/fu/mul/mul_input_record.py
+++ b/src/soc/fu/mul/mul_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 
 class CompMULOpSubset(Record):
 
 
 class CompMULOpSubset(Record):


@@ -11,7 +11,7 @@ class CompMULOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index 9f3d69632cf33b5410083907bde83f498bfc3b9b..0fc718049e92c209b6f861d5731e544658d5f0e6 100644 (file)
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -5,7 +5,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DivMulOutputData
 from soc.fu.mul.pipe_data import MulOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.div.pipe_data import DivMulOutputData
 from soc.fu.mul.pipe_data import MulOutputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 class MulMainStage3(PipeModBase):
 
 
 class MulMainStage3(PipeModBase):


@@ -38,10 +38,10 @@ class MulMainStage3(PipeModBase):
         # OP_MUL_nnn - select hi32/hi64/lo64 from result
         with m.Switch(op.insn_type):
             # hi-32 replicated twice
         # OP_MUL_nnn - select hi32/hi64/lo64 from result
         with m.Switch(op.insn_type):
             # hi-32 replicated twice

-            with m.Case(InternalOp.OP_MUL_H32):
+            with m.Case(MicrOp.OP_MUL_H32):

                 comb += o.data.eq(Repl(mul_o[32:64], 2))
             # hi-64 
                 comb += o.data.eq(Repl(mul_o[32:64], 2))
             # hi-64 

-            with m.Case(InternalOp.OP_MUL_H64):
+            with m.Case(MicrOp.OP_MUL_H64):

                 comb += o.data.eq(mul_o[64:128])
             # lo-64 - overflow
             with m.Default():
                 comb += o.data.eq(mul_o[64:128])
             # lo-64 - overflow
             with m.Default():

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index b85c0e04fbdb604f830a39e85a44b9a317423710..56d3fed6961abf07dc4c0774d28c733baebfc17c 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 9b083a54564bf241a36fa419a227c813f6854559..685b221f5641e20628b00eeafa9f7cb10f076133 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -14,7 +14,7 @@ from nmigen.cli import rtlil
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import unittest
 
 
 import unittest
 
 


@@ -74,7 +74,7 @@ class Driver(Elaboratable):
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
 

-            with m.Case(InternalOp.OP_SHL):
+            with m.Case(MicrOp.OP_SHL):

                 comb += Assume(ra == 0)
                 with m.If(rec.is_32bit):
                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
                 comb += Assume(ra == 0)
                 with m.If(rec.is_32bit):
                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))


@@ -82,7 +82,7 @@ class Driver(Elaboratable):
                 with m.Else():
                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
 
                 with m.Else():
                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
 

-            with m.Case(InternalOp.OP_SHR):
+            with m.Case(MicrOp.OP_SHR):

                 comb += Assume(ra == 0)
                 with m.If(~rec.is_signed):
                     with m.If(rec.is_32bit):
                 comb += Assume(ra == 0)
                 with m.If(~rec.is_signed):
                     with m.If(rec.is_32bit):


@@ -97,11 +97,11 @@ class Driver(Elaboratable):
                     with m.Else():
                         comb += Assert(o == (a_signed >> b[0:7]))
             #TODO
                     with m.Else():
                         comb += Assert(o == (a_signed >> b[0:7]))
             #TODO

-            with m.Case(InternalOp.OP_RLC):
+            with m.Case(MicrOp.OP_RLC):

                 pass
                 pass

-            with m.Case(InternalOp.OP_RLCR):
+            with m.Case(MicrOp.OP_RLCR):

                 pass
                 pass

-            with m.Case(InternalOp.OP_RLCL):
+            with m.Case(MicrOp.OP_RLCL):

                 pass
             with m.Default():
                 comb += o_ok.eq(0)
                 pass
             with m.Default():
                 comb += o_ok.eq(0)

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index ae9d59fbb271f181110bd1c33bc8e2052eb89c2a..f27134c4d76473166ee155e4391e3d470d68cd22 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -7,7 +7,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalOutputData
 from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.fu.logical.pipe_data import LogicalOutputData
 from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 from ieee754.part.partsig import PartitionedSignal

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 from soc.fu.shift_rot.rotator import Rotator
 
 from soc.decoder.power_fields import DecodeFields
 from soc.fu.shift_rot.rotator import Rotator
 
 from soc.decoder.power_fields import DecodeFields


@@ -62,11 +62,11 @@ class ShiftRotMainStage(PipeModBase):
         # instruction rotate type
         mode = Signal(3, reset_less=True)
         with m.Switch(op.insn_type):
         # instruction rotate type
         mode = Signal(3, reset_less=True)
         with m.Switch(op.insn_type):

-            with m.Case(InternalOp.OP_SHL):  comb += mode.eq(0b000)
-            with m.Case(InternalOp.OP_SHR):  comb += mode.eq(0b001) # R-shift
-            with m.Case(InternalOp.OP_RLC):  comb += mode.eq(0b110) # clear LR
-            with m.Case(InternalOp.OP_RLCL): comb += mode.eq(0b010) # clear L
-            with m.Case(InternalOp.OP_RLCR): comb += mode.eq(0b100) # clear R
+            with m.Case(MicrOp.OP_SHL):  comb += mode.eq(0b000)
+            with m.Case(MicrOp.OP_SHR):  comb += mode.eq(0b001) # R-shift
+            with m.Case(MicrOp.OP_RLC):  comb += mode.eq(0b110) # clear LR
+            with m.Case(MicrOp.OP_RLCL): comb += mode.eq(0b010) # clear L
+            with m.Case(MicrOp.OP_RLCR): comb += mode.eq(0b100) # clear R

             with m.Default():
                 comb += o.ok.eq(0) # otherwise disable
 
             with m.Default():
                 comb += o.ok.eq(0) # otherwise disable
 

diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py
index da055538e5db1704ac9f31b11677c8a29d6d41de..6b0c7eb9f546ccdd2a93eb8cf574582f6efa7ec0 100644 (file)
--- a/src/soc/fu/shift_rot/sr_input_record.py
+++ b/src/soc/fu/shift_rot/sr_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn

 
 
 class CompSROpSubset(Record):
 
 
 class CompSROpSubset(Record):


@@ -11,7 +11,7 @@ class CompSROpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index e2234e67edaca195601de8dcc7ea4b7b07064842..f4261b62a2b2d104c9edfa88262f27a97d9498a3 100644 (file)
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -7,7 +7,7 @@
 from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
 from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData

-from soc.decoder.power_enums import InternalOp, SPR, XER_bits
+from soc.decoder.power_enums import MicrOp, SPR, XER_bits

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -45,7 +45,7 @@ class SPRMainStage(PipeModBase):
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### MTSPR ####
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### MTSPR ####

-            with m.Case(InternalOp.OP_MTSPR):
+            with m.Case(MicrOp.OP_MTSPR):

                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1):


@@ -67,7 +67,7 @@ class SPRMainStage(PipeModBase):
                     # slow SPRs TODO
 
             # move from SPRs
                     # slow SPRs TODO
 
             # move from SPRs

-            with m.Case(InternalOp.OP_MFSPR):
+            with m.Case(MicrOp.OP_MFSPR):

                 comb += o.ok.eq(1)
                 with m.Switch(spr):
                     # fast SPRs first
                 comb += o.ok.eq(1)
                 with m.Switch(spr):
                     # fast SPRs first

diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py
index 8dfce155d349b445a56a902dd5811d112592fb16..84599a98163c3049c2e29dda7fc0d1d1fbb2a8af 100644 (file)
--- a/src/soc/fu/spr/spr_input_record.py
+++ b/src/soc/fu/spr/spr_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)

 
 
 class CompSPROpSubset(Record):
 
 
 class CompSPROpSubset(Record):


@@ -11,7 +11,7 @@ class CompSPROpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('insn', 32),
                   ('is_32bit', 1),
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('is_32bit', 1),

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index d879d439ceea0452a85ce49ba558871808fde367..c05ea950fe794f8eeb65d8d373daeda0055df782 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 0ddb2823f13243ba8a54aa501b2c641514092980..769ae86386da336f04abdfe7a0477cf3339c9c61 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -14,7 +14,7 @@ from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
 from soc.fu.branch.main_stage import br_ext
 from nmutil.extend import exts
 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
 from soc.fu.branch.main_stage import br_ext

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange


@@ -146,7 +146,7 @@ class TrapMainStage(PipeModBase):
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### trap ####
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### trap ####

-            with m.Case(InternalOp.OP_TRAP):
+            with m.Case(MicrOp.OP_TRAP):

                 # trap instructions (tw, twi, td, tdi)
                 with m.If(should_trap):
                     # generate trap-type program interrupt
                 # trap instructions (tw, twi, td, tdi)
                 with m.If(should_trap):
                     # generate trap-type program interrupt


@@ -164,7 +164,7 @@ class TrapMainStage(PipeModBase):
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR

-            with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR):
+            with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):

                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 # start with copy of msr
                 comb += msr_o.eq(msr_i)
                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 # start with copy of msr
                 comb += msr_o.eq(msr_i)


@@ -181,12 +181,12 @@ class TrapMainStage(PipeModBase):
                 comb += msr_o.ok.eq(1)
 
             # move from MSR
                 comb += msr_o.ok.eq(1)
 
             # move from MSR

-            with m.Case(InternalOp.OP_MFMSR):
+            with m.Case(MicrOp.OP_MFMSR):

                 # TODO: some of the bits need zeroing?  apparently not
                 comb += o.data.eq(msr_i)
                 comb += o.ok.eq(1)
 
                 # TODO: some of the bits need zeroing?  apparently not
                 comb += o.data.eq(msr_i)
                 comb += o.ok.eq(1)
 

-            with m.Case(InternalOp.OP_RFID):
+            with m.Case(MicrOp.OP_RFID):

                 # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
                 # XXX f_out.priv_mode <= not b_in(MSR.PR);
 
                 # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
                 # XXX f_out.priv_mode <= not b_in(MSR.PR);
 


@@ -210,7 +210,7 @@ class TrapMainStage(PipeModBase):
                 comb += msr_o.ok.eq(1)
 
             # OP_SC
                 comb += msr_o.ok.eq(1)
 
             # OP_SC

-            with m.Case(InternalOp.OP_SC):
+            with m.Case(MicrOp.OP_SC):

                 # TODO: scv must generate illegal instruction.  this is
                 # the decoder's job, not ours, here.
 
                 # TODO: scv must generate illegal instruction.  this is
                 # the decoder's job, not ours, here.
 


@@ -218,7 +218,7 @@ class TrapMainStage(PipeModBase):
                 self.trap(m, 0xc00, cia_i+4)
 
             # TODO (later)
                 self.trap(m, 0xc00, cia_i+4)
 
             # TODO (later)

-            #with m.Case(InternalOp.OP_ADDPCIS):
+            #with m.Case(MicrOp.OP_ADDPCIS):

             #    pass
 
         comb += self.o.ctx.eq(self.i.ctx)
             #    pass
 
         comb += self.o.ctx.eq(self.i.ctx)

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 552be8f421a01c47a1fac46c4e398e9c43d42a15..44fbba6aff3ac75a4ec98ca25f834c334a087787 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -6,7 +6,7 @@ import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)

-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)

 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 9c9a53c4bc1ab9157dc3da13719bf5566f64082b..84715f82b519ab4fc835bd01ac86666422a2eb71 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,6 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
 from nmigen.hdl.rec import Record, Layout
 

-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)

 
 
 class CompTrapOpSubset(Record):
 
 
 class CompTrapOpSubset(Record):


@@ -11,7 +11,7 @@ class CompTrapOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
     grab subsets.
     """
     def __init__(self, name=None):

-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),

                   ('fn_unit', Function),
                   ('insn', 32),
                   ('is_32bit', 1),
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('is_32bit', 1),

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index ceac442cdf2f30ac10375f171d18addb30a16217..740cc9908b752cf9f45970db62abc8401b1ae8e0 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -32,7 +32,7 @@ from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
 from soc.config.test.test_loadstore import TestMemPspec

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 import operator
 
 
 import operator
 
 


@@ -157,10 +157,10 @@ class NonProductionCore(Elaboratable):
         with m.If(can_run):
             with m.Switch(dec2.e.do.insn_type):
             # check for ATTN: halt if true
         with m.If(can_run):
             with m.Switch(dec2.e.do.insn_type):
             # check for ATTN: halt if true

-                with m.Case(InternalOp.OP_ATTN):
+                with m.Case(MicrOp.OP_ATTN):

                     m.d.sync += core_stopped.eq(1)
 
                     m.d.sync += core_stopped.eq(1)
 

-                with m.Case(InternalOp.OP_NOP):
+                with m.Case(MicrOp.OP_NOP):

                     sync += counter.eq(2)
                     comb += self.busy_o.eq(1)
 
                     sync += counter.eq(2)
                     comb += self.busy_o.eq(1)
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 2d7ae5e0f582e2a2f53856d8fa30136e24809f41..0f90943d85b0cdcbaed6137573f1afe27a797c85 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -24,7 +24,7 @@ from soc.regfile.regfiles import FastRegs
 from soc.simple.core import NonProductionCore
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.ifetch import ConfigFetchUnit
 from soc.simple.core import NonProductionCore
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.ifetch import ConfigFetchUnit

-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp

 
 
 class TestIssuer(Elaboratable):
 
 
 class TestIssuer(Elaboratable):


@@ -142,7 +142,7 @@ class TestIssuer(Elaboratable):
                     with m.If(core.core_terminated_o):
                         m.next = "IDLE" # back to idle, immediately (OP_ATTN)
                     with m.Else():
                     with m.If(core.core_terminated_o):
                         m.next = "IDLE" # back to idle, immediately (OP_ATTN)
                     with m.Else():

-                        with m.If(insn_type != InternalOp.OP_NOP):
+                        with m.If(insn_type != MicrOp.OP_NOP):

                             comb += core_ivalid_i.eq(1) # instruction is valid
                         comb += core_opcode_i.eq(ilatch) # actual opcode
                         with m.If(self.fast_nia.wen):
                             comb += core_ivalid_i.eq(1) # instruction is valid
                         comb += core_opcode_i.eq(ilatch) # actual opcode
                         with m.If(self.fast_nia.wen):

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index a6f186016505f5ed13cf41cae33dfdc192f40944..04278c30ca7fcdf5301a8cead03b4dacf4dafc5f 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,

diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py
index fb5ed7684d81b8f2f9d3901e820a270ce415e41f..2ff1e0069f4608101f9a7bd2b554b75fc0066705 100644 (file)
--- a/src/soc/simulator/test_helloworld_sim.py
+++ b/src/soc/simulator/test_helloworld_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,

diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index 00c51a4e6568697ef3452809b1e68118581154fb..ef117c3a2d127f25087091ac63786002fdc41b42 100644 (file)
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index d1e65f4fcdb017f2679dde9f4d6ba3da18035fa7..dae60ceaf0aad1c486e460d29d4f8b9377e7c242 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,

diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py
index dfb4faa277281f67018da30e3460f82d5175abc6..d535cf1a76695443d27ccd5fc96c256073b9b887 100644 (file)
--- a/src/soc/simulator/test_trap_sim.py
+++ b/src/soc/simulator/test_trap_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,

                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,