This extreme power and flexibility comes down to the fact that SVP64
is not actually a Vector ISA: it is a loop-abstraction-concept that
This extreme power and flexibility comes down to the fact that SVP64
is not actually a Vector ISA: it is a loop-abstraction-concept that
"normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides),
note that the VL loop is outer and the SUBVL loop inner:
"normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides),
note that the VL loop is outer and the SUBVL loop inner:
For pack/unpack (again, no elwidth overrides), note that now there is the
option to swap the SUBVL and VL loop orders.
For pack/unpack (again, no elwidth overrides), note that now there is the
option to swap the SUBVL and VL loop orders.