create SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 108a730d5db8d47d7c7267104af3167b4a9efc24..c89fed93802677fd40fc4948da874f8859ffa50f 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -223,10 +223,18 @@ class EXTRA3:
 EXTRA3_SIZE = 9
 
 
 EXTRA3_SIZE = 9
 
 

+# SVP64 ReMapped Field (from v3.1 EXT001 Prefix)

 class SVP64P:
     OPC = range(0, 6)
     SVP64_7_9 = [7, 9]
     RM = [6, 8] + list(range(10, 32))
 
 class SVP64P:
     OPC = range(0, 6)
     SVP64_7_9 = [7, 9]
     RM = [6, 8] + list(range(10, 32))
 

-
+# 24 bits in RM

 SVP64P_SIZE = 24
 SVP64P_SIZE = 24

+
+
+# CR SVP64 offsets
+class SVP64CROffs:
+    CR0 = 0    # TODO: increase when CRs are expanded to 128
+    CR1 = 1    # TODO: increase when CRs are expanded to 128
+

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 676a87d1a74cd086f5bf11ec138718b29cccd249..388b7df96d69253845d95b70df7d2dd85a68ccd7 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -12,6 +12,7 @@ from soc.decoder.orderedset import OrderedSet
 from soc.decoder.isa.all import ISA
 from soc.decoder.isa.test_caller import Register, run_tst
 from soc.sv.trans.svp64 import SVP64Asm
 from soc.decoder.isa.all import ISA
 from soc.decoder.isa.test_caller import Register, run_tst
 from soc.sv.trans.svp64 import SVP64Asm

+from soc.consts import SVP64CROffs

 from copy import deepcopy
 
 class DecoderTestCase(FHDLTestCase):
 from copy import deepcopy
 
 class DecoderTestCase(FHDLTestCase):


@@ -134,8 +135,10 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
             # XXX TODO, these need to move to higher range (offset)
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
             # XXX TODO, these need to move to higher range (offset)

-            CR0 = sim.crl[0].get_range().value
-            CR1 = sim.crl[1].get_range().value
+            cr0_idx = SVP64CROffs.CR0
+            cr1_idx = SVP64CROffs.CR1
+            CR0 = sim.crl[cr0_idx].get_range().value
+            CR1 = sim.crl[cr1_idx].get_range().value

             print ("CR0", CR0)
             print ("CR1", CR1)
             self._check_regs(sim, expected_regs)
             print ("CR0", CR0)
             print ("CR1", CR1)
             self._check_regs(sim, expected_regs)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index e3b6175dd735110a3a9439f912d495ea6f2b2b25..27ce810acec850618c2bfd2c114c83f0cd334a50 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -28,7 +28,7 @@ from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
                                          Decode2ToOperand)
 from soc.sv.svp64 import SVP64Rec
 from soc.consts import (MSR, sel, SPEC, EXTRA2, EXTRA3, SVP64P, field,
                                          Decode2ToOperand)
 from soc.sv.svp64 import SVP64Rec
 from soc.consts import (MSR, sel, SPEC, EXTRA2, EXTRA3, SVP64P, field,

-                        SPEC_SIZE, SPECb, SPEC_AUG_SIZE)
+                        SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)

 
 from soc.regfile.regfiles import FastRegs
 from soc.consts import TT
 
 from soc.regfile.regfiles import FastRegs
 from soc.consts import TT


@@ -1199,11 +1199,14 @@ class PowerDecode2(PowerDecodeSubset):
             comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
             with m.If(svdec.isvec):
                 # check if this is CR0 or CR1: treated differently
             comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
             with m.If(svdec.isvec):
                 # check if this is CR0 or CR1: treated differently

-                # (does not "listen" to EXTRA2/3 spec
+                # (does not "listen" to EXTRA2/3 spec for a start)
+                # also: the CRs start from completely different locations

                 with m.If(cr.sv_override == 1): # CR0
                 with m.If(cr.sv_override == 1): # CR0

-                    comb += to_reg.data.eq(srcstep+0) # XXX TODO CR0 offset
+                    offs = SVP64CROffs.CR0
+                    comb += to_reg.data.eq(srcstep+offs)

                 with m.Elif(cr.sv_override == 2): # CR1
                 with m.Elif(cr.sv_override == 2): # CR1

-                    comb += to_reg.data.eq(srcstep+1) # XXX TODO CR1 offset
+                    offs = SVP64CROffs.CR1
+                    comb += to_reg.data.eq(srcstep+1)

                 with m.Else():
                     comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output
             with m.Else():
                 with m.Else():
                     comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output
             with m.Else():