+* `SVi` - bits 16-22 - an immediate operand for setting MVL and/or VL
+* `ms` - bit 23 - allows for setting of MVL
+* `vs` - bit 24 - allows for setting of VL
+* `vf` - bit 25 - sets "Vertical First Mode".
+
+Note that in immediate setting mode VL and MVL start from **one**
+but that this is compensated for in the assembly notation.
+i.e. that an immediate value of 1 in assembler notation
+actually places the value 0b0000000 in the `SVi` field bits:
+on execution the `setvl` instruction adds one to the decoded
+`SVi` field bits, resulting in
+VL/MVL being set to 1. This allows VL to be set to values
+ranging from 1 to 128 with only 7 bits instead of 8.
+Setting VL/MVL
+to 0 would result in all Vector operations becoming `nop`. If this is
+truly desired (nop behaviour) then setting VL and MVL to zero is to be
+done via the [[SVSTATE SPR|sv/sprs]].
+
+Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
+
+ setvli VL=8 : setvl r0, r0, VL=8, vf=0, vs=1, ms=0
+ setvli. VL=8 : setvl. r0, r0, VL=8, vf=0, vs=1, ms=0
+ setmvli MVL=8 : setvl r0, r0, MVL=8, vf=0, vs=0, ms=1
+ setmvli. MVL=8 : setvl. r0, r0, MVL=8, vf=0, vs=0, ms=1
+
+Additional pseudo-op for obtaining VL without modifying it (or any state):
+
+ getvl r5 : setvl r5, r0, vf=0, vs=0, ms=0
+ getvl. r5 : setvl. r5, r0, vf=0, vs=0, ms=0
+