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update explanatory comments
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 07:52:14 +0000
(08:52 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 07:52:14 +0000
(08:52 +0100)
src/ieee754/fpmul/mul1.py
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diff --git
a/src/ieee754/fpmul/mul1.py
b/src/ieee754/fpmul/mul1.py
index 841efcdfed3df98d4fd0aebadb7feb3c3a47791e..6d2f9ff4c0994ad16859b6992c87bfa4c905680e 100644
(file)
--- a/
src/ieee754/fpmul/mul1.py
+++ b/
src/ieee754/fpmul/mul1.py
@@
-30,14
+30,16
@@
class FPMulStage1Mod(FPState, Elaboratable):
""" links module to inputs and outputs
"""
m.submodules.mul1 = self
""" links module to inputs and outputs
"""
m.submodules.mul1 = self
- #m.submodules.mul1_out_overflow = self.o.of
-
m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.z.eq(self.i.z)
with m.If(~self.i.out_do_z):
m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.z.eq(self.i.z)
with m.If(~self.i.out_do_z):
+ # results are in the range 0.25 to 0.999999999999
+ # sometimes the MSB will be zero, (0.5 * 0.5 = 0.25 which
+ # in binary is 0b010000) so to compensate for that we have
+ # to shift the mantissa up (and reduce the exponent by 1)
p = Signal(len(self.i.product), reset_less=True)
with m.If(self.i.product[-1]):
m.d.comb += p.eq(self.i.product)
p = Signal(len(self.i.product), reset_less=True)
with m.If(self.i.product[-1]):
m.d.comb += p.eq(self.i.product)
@@
-45,13
+47,16
@@
class FPMulStage1Mod(FPState, Elaboratable):
# get 1 bit of extra accuracy if the mantissa top bit is zero
m.d.comb += p.eq(self.i.product<<1)
m.d.comb += self.o.z.e.eq(self.i.z.e-1)
# get 1 bit of extra accuracy if the mantissa top bit is zero
m.d.comb += p.eq(self.i.product<<1)
m.d.comb += self.o.z.e.eq(self.i.z.e-1)
+
+ # top bits are mantissa, then guard and round, and the rest of
+ # the product is sticky
mw = self.o.z.m_width
m.d.comb += [
mw = self.o.z.m_width
m.d.comb += [
- self.o.z.m.eq(p[mw+2:]),
- self.o.of.m0.eq(p[mw+2]),
- self.o.of.guard.eq(p[mw+1]),
- self.o.of.round_bit.eq(p[mw]),
- self.o.of.sticky.eq(p[0:mw].bool())
+ self.o.z.m.eq(p[mw+2:]),
# mantissa
+ self.o.of.m0.eq(p[mw+2]),
# copy of LSB
+ self.o.of.guard.eq(p[mw+1]),
# guard
+ self.o.of.round_bit.eq(p[mw]),
# round
+ self.o.of.sticky.eq(p[0:mw].bool())
# sticky
]
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
]
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)