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diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index f48474d8729251f934232d8d2ee29d7aed9547e4..310c20cb4a2ba0eb2b9e379f238f412b7e9f0fd9 100644 (file)
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -2,7 +2,22 @@
 
 **Proposal: Add the following Definition to Section 1.3.1 of Book I**
 
 
 **Proposal: Add the following Definition to Section 1.3.1 of Book I**
 

-Definition of "UnVectoriseable":
+**Definition of SVP64 Prefixing:**
+
+In its simpest form, SVP64 is a 32-bit Prefix conceptually similar to Intel 8086 `REP`
+instruction that both augments its following Defined Word Suffix, and also may
+repeat that instruction with optional sequential register offsets from those given in the 
+Suffix. More advanced features add predication, element-width overrides, and Vertical-First
+Mode.
+
+**Definition of SVP64Single Prefixing:**
+
+A 32-bit Prefix in front of a Defined Word that extends register numbers
+(allows larger register files), adds single-bit predication, element-width overrides,
+and optionally adds Saturation to Arithmetic instructions that normally would not
+have it.  *SVP64 is in Draft only* and is yet to be defined.
+
+**Definition of "UnVectoriseable":**

 
 Any operation that inherently makes no sense if repeated (through SVP64
 Prefixing) is termed "UnVectoriseable" or "UnVectorised".  Examples
 
 Any operation that inherently makes no sense if repeated (through SVP64
 Prefixing) is termed "UnVectoriseable" or "UnVectorised".  Examples