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lkcl
<lkcl@web>
Sat, 18 Sep 2021 11:25:07 +0000
(12:25 +0100)
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IkiWiki
<ikiwiki.info>
Sat, 18 Sep 2021 11:25:07 +0000
(12:25 +0100)
openpower/sv/svp64.mdwn
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a/openpower/sv/svp64.mdwn
b/openpower/sv/svp64.mdwn
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openpower/sv/svp64.mdwn
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openpower/sv/svp64.mdwn
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Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
Mode is an augmentation of SV behaviour. Different types of
instructions have different needs, similar to Power ISA
v3.1 64 bit prefix 8LS and MTRR formats apply to different
Mode is an augmentation of SV behaviour. Different types of
instructions have different needs, similar to Power ISA
v3.1 64 bit prefix 8LS and MTRR formats apply to different
-instruction types
+instruction types. Modes include Reduction, Iteration, arithmetic
+saturation, and Fail-First. More specific details in each
+section and in the [[svp64/appendix]]
* For condition register operations see [[sv/cr_ops]]
* For LD/ST Modes, see [[sv/ldst]].
* For condition register operations see [[sv/cr_ops]]
* For LD/ST Modes, see [[sv/ldst]].