+ @classmethod
+ def add_verilog_source(cls, verilog_src_dir, platform):
+ # add each of the verilog sources, needed for when doing platform.build
+ for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
+ 'uart_top.v', 'timescale.v', 'uart_receiver.v',
+ 'uart_sync_flops.v', 'uart_transmitter.v',
+ 'uart_debug_if.v', 'uart_regs.v',
+ 'uart_tfifo.v', 'uart_wb.v'
+ ]:
+ # prepend the src directory to each filename, add its contents
+ fullname = os.path.join(verilog_src_dir, fname)
+ with open(fullname) as f:
+ platform.add_file(fullname, f)
+