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pass self.pi.is_dcbz to request
author
Tobias Platen
<tplaten@posteo.de>
Sun, 11 Jul 2021 16:18:13 +0000
(18:18 +0200)
committer
Tobias Platen
<tplaten@posteo.de>
Sun, 11 Jul 2021 16:18:13 +0000
(18:18 +0200)
src/soc/fu/ldst/loadstore.py
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diff --git
a/src/soc/fu/ldst/loadstore.py
b/src/soc/fu/ldst/loadstore.py
index 7cff898743703d902cee7ddeaf0028a7a514cc23..d4db098c3e403c3904bd3144080dc160ea3894c7 100644
(file)
--- a/
src/soc/fu/ldst/loadstore.py
+++ b/
src/soc/fu/ldst/loadstore.py
@@
-21,7
+21,7
@@
from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
Record, Memory,
Const)
from nmutil.iocontrol import RecordObject
Record, Memory,
Const)
from nmutil.iocontrol import RecordObject
-from nmutil.util import rising_edge
+from nmutil.util import rising_edge
, Display
from enum import Enum, unique
from soc.experiment.dcache import DCache
from enum import Enum, unique
from soc.experiment.dcache import DCache
@@
-126,6
+126,11
@@
class LoadStore1(PortInterfaceBase):
m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem ==> priv
m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
m.d.comb += self.req.align_intr.eq(misalign)
m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem ==> priv
m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
m.d.comb += self.req.align_intr.eq(misalign)
+
+ dcbz = self.pi.is_dcbz
+ m.d.comb += Display("is_dcbz %x",dcbz)
+ m.d.comb += self.req.dcbz.eq(dcbz)
+
# option to disable the cache entirely for write
if self.disable_cache:
m.d.comb += self.req.nc.eq(1)
# option to disable the cache entirely for write
if self.disable_cache:
m.d.comb += self.req.nc.eq(1)