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move DMI stuff to separate function in issuer.py
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 7 Mar 2021 11:34:32 +0000
(11:34 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 7 Mar 2021 11:34:32 +0000
(11:34 +0000)
src/soc/simple/issuer.py
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diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index 25eaa0360083d4a05dd84956bf45c6928d47e2f2..f13f5672de12722ebaf2abc324b4914543a07d7d 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-615,6
+615,20
@@
class TestIssuerInternal(Elaboratable):
# this bit doesn't have to be in the FSM: connect up to read
# regfiles on demand from DMI
# this bit doesn't have to be in the FSM: connect up to read
# regfiles on demand from DMI
+ self.do_dmi(m, dbg)
+
+ # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
+ # (which uses that in PowerDecoder2 to raise 0x900 exception)
+ self.tb_dec_fsm(m, cur_state.dec)
+
+ return m
+
+ def do_dmi(self, m, dbg):
+ comb = m.d.comb
+ sync = m.d.sync
+ dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
+ intrf = self.core.regs.rf['int']
+
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
# XXX should this be combinatorial? sync better?
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
# XXX should this be combinatorial? sync better?
@@
-650,12
+664,6
@@
class TestIssuerInternal(Elaboratable):
comb += d_xer.data.eq(self.xer_r.data_o)
comb += d_xer.ack.eq(1)
comb += d_xer.data.eq(self.xer_r.data_o)
comb += d_xer.ack.eq(1)
- # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
- # (which uses that in PowerDecoder2 to raise 0x900 exception)
- self.tb_dec_fsm(m, cur_state.dec)
-
- return m
-
def tb_dec_fsm(self, m, spr_dec):
"""tb_dec_fsm
def tb_dec_fsm(self, m, spr_dec):
"""tb_dec_fsm