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Make rv64mi-p-ecall work when U-mode is not present
author
Andrew Waterman
<andrew@sifive.com>
Fri, 10 Nov 2017 03:25:22 +0000
(19:25 -0800)
committer
Andrew Waterman
<andrew@sifive.com>
Fri, 10 Nov 2017 03:26:45 +0000
(19:26 -0800)
isa/rv64si/scall.S
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diff --git
a/isa/rv64si/scall.S
b/isa/rv64si/scall.S
index cb97635bab7a70b8d26472bd72661858801a8768..1f5e6b79fa286f9d486f1274f320fadd2e1516d2 100644
(file)
--- a/
isa/rv64si/scall.S
+++ b/
isa/rv64si/scall.S
@@
-26,6
+26,23
@@
RVTEST_CODE_BEGIN
li TESTNUM, 2
li TESTNUM, 2
+ # This is the expected trap code.
+ li t1, CAUSE_USER_ECALL
+
+#ifdef __MACHINE_MODE
+ # If running in M mode, use mstatus.MPP to check existence of U mode.
+ # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+ li t0, MSTATUS_MPP
+ csrc mstatus, t0
+ csrr t1, mstatus
+ and t0, t0, t1
+ beqz t0, 1f
+
+ # If U mode doesn't exist, mcause should indicate ECALL from M mode.
+ li t1, CAUSE_MACHINE_ECALL
+#endif
+
+1:
li t0, SSTATUS_SPP
csrc sstatus, t0
la t0, 1f
li t0, SSTATUS_SPP
csrc sstatus, t0
la t0, 1f
@@
-42,7
+59,6
@@
RVTEST_CODE_BEGIN
.align 2
.global stvec_handler
stvec_handler:
.align 2
.global stvec_handler
stvec_handler:
- li t1, CAUSE_USER_ECALL
csrr t0, scause
bne t0, t1, fail
j pass
csrr t0, scause
bne t0, t1, fail
j pass