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testcase for dcbz
author
Tobias Platen
<tplaten@posteo.de>
Tue, 17 Nov 2020 19:20:16 +0000
(20:20 +0100)
committer
Tobias Platen
<tplaten@posteo.de>
Tue, 17 Nov 2020 19:20:16 +0000
(20:20 +0100)
src/soc/fu/mmu/test/test_pipe_caller.py
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diff --git
a/src/soc/fu/mmu/test/test_pipe_caller.py
b/src/soc/fu/mmu/test/test_pipe_caller.py
index 373cd658becd4a9cb41876203686b11536b7f7dc..f45bc2dcaaec687a2a7d8742940c671ea3e7ab40 100644
(file)
--- a/
src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/
src/soc/fu/mmu/test/test_pipe_caller.py
@@
-74,24
+74,27
@@
class MMUTestCase(TestAccumulatorBase):
def case_1_mmu(self):
# test case for MTSPR, MFSPR, DCBZ and TLBIE.
#lst = ["dcbz 2,3"] not yet implemented
def case_1_mmu(self):
# test case for MTSPR, MFSPR, DCBZ and TLBIE.
#lst = ["dcbz 2,3"] not yet implemented
- lst = ["mtspr 18, 1", # DSISR
- "mtspr 19, 2", # DAR
- "mtspr 26, 3", # SRR0
- "mtspr 27, 4", # SRR1
+ lst = [
#
"mtspr 18, 1", # DSISR
+
#
"mtspr 19, 2", # DAR
+
#
"mtspr 26, 3", # SRR0
+
#
"mtspr 27, 4", # SRR1
- "mfspr 18, 1", # DSISR
+
#
"mfspr 18, 1", # DSISR
#"mfspr 19, 2", # DAR
#"mfspr 19, 2", # DAR
- "mfspr 26, 3", # SRR0
+
#
"mfspr 26, 3", # SRR0
#"mfspr 27, 4", # SRR1
#next two need to be added to the simulator
#"mfspr 27, 4", # SRR1
#next two need to be added to the simulator
-
#
"dcbz 5,6" # Data Cache Block set to Zero - RA,RB (hangs)
- "tlbie 1,1,1,1,1" #does not hang -- not verified yet
+ "dcbz 5,6" # Data Cache Block set to Zero - RA,RB (hangs)
+
#
"tlbie 1,1,1,1,1" #does not hang -- not verified yet
]
initial_regs = [0] * 32
initial_regs[1] = 0xBADCAB1E
initial_regs[2] = 0xDEADC0DE
]
initial_regs = [0] * 32
initial_regs[1] = 0xBADCAB1E
initial_regs[2] = 0xDEADC0DE
+ initial_regs[5] = 0x100
+ initial_regs[6] = 0x100
+
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0xe00c0000}
self.add_case(Program(lst, bigendian),
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0xe00c0000}
self.add_case(Program(lst, bigendian),