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update pi_dcbz function
author
Tobias Platen
<tplaten@posteo.de>
Wed, 21 Jul 2021 17:57:55 +0000
(19:57 +0200)
committer
Tobias Platen
<tplaten@posteo.de>
Wed, 21 Jul 2021 17:57:55 +0000
(19:57 +0200)
src/soc/config/test/test_pi2ls.py
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diff --git
a/src/soc/config/test/test_pi2ls.py
b/src/soc/config/test/test_pi2ls.py
index 2c4b89cc41a429c1429959a3ba8d2881d8a0d1bf..4bdd11844c7d98e0f267b6453884125bec6c2482 100644
(file)
--- a/
src/soc/config/test/test_pi2ls.py
+++ b/
src/soc/config/test/test_pi2ls.py
@@
-67,14
+67,13
@@
def pi_st(port1, addr, data, datalen, msr_pr=0):
yield from wait_busy(port1, True) # wait while busy
# copy of pi_st
yield from wait_busy(port1, True) # wait while busy
# copy of pi_st
-def pi_dcbz(port1, addr,
data, datalen,
msr_pr=0):
+def pi_dcbz(port1, addr, msr_pr=0):
# have to wait until not busy
yield from wait_busy(port1, no=False,debug="busy") # wait until not busy
# set up a ST on the port. address first:
yield port1.is_st_i.eq(1) # indicate ST
# have to wait until not busy
yield from wait_busy(port1, no=False,debug="busy") # wait until not busy
# set up a ST on the port. address first:
yield port1.is_st_i.eq(1) # indicate ST
- yield port1.data_len.eq(datalen) # ST length (1/2/4/8)
yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real)
yield port1.is_dcbz.eq(1) # set dcbz
yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real)
yield port1.is_dcbz.eq(1) # set dcbz
@@
-82,14
+81,18
@@
def pi_dcbz(port1, addr, data, datalen, msr_pr=0):
yield port1.addr.data.eq(addr) # set address
yield port1.addr.ok.eq(1) # set ok
yield Settle()
yield port1.addr.data.eq(addr) # set address
yield port1.addr.ok.eq(1) # set ok
yield Settle()
- yield from wait_addr(port1,debug="addr") # wait until addr ok
- # yield # not needed, just for checking
- # yield # not needed, just for checking
- # assert "ST" for one cycle (required by the API)
- yield port1.st.data.eq(data)
+
+ # guess: this is not needed
+ # yield from wait_addr(port1,debug="addr") # wait until addr ok
+
+ # just write some dummy data -- remove
+ print("dummy write begin")
+ yield port1.st.data.eq(0)
yield port1.st.ok.eq(1)
yield
yield port1.st.ok.eq(0)
yield port1.st.ok.eq(1)
yield
yield port1.st.ok.eq(0)
+ print("dummy write end")
+
yield from wait_busy(port1, no=True, debug="not_busy") # wait while busy
# can go straight to reset.
yield from wait_busy(port1, no=True, debug="not_busy") # wait while busy
# can go straight to reset.