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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 17 Apr 2021 08:03:44 +0000
(09:03 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 17 Apr 2021 08:03:44 +0000
(09:03 +0100)
c4m/nmigen/jtag/tap.py
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diff --git
a/c4m/nmigen/jtag/tap.py
b/c4m/nmigen/jtag/tap.py
index 525b5311748973a4b287516154e8759b4e3f0710..84adf9d57fb2463c7f172533065f5ee5d5494341 100755
(executable)
--- a/
c4m/nmigen/jtag/tap.py
+++ b/
c4m/nmigen/jtag/tap.py
@@
-119,6
+119,7
@@
class _FSM(Elaboratable):
return m
return m
+
class _IRBlock(Elaboratable):
"""TAP subblock for handling the IR shift register"""
def __init__(self, *, ir_width, cmd_idcode,
class _IRBlock(Elaboratable):
"""TAP subblock for handling the IR shift register"""
def __init__(self, *, ir_width, cmd_idcode,
@@
-151,12
+152,14
@@
class _IRBlock(Elaboratable):
return m
return m
+
class IOType(Enum):
In = auto()
Out = auto()
TriOut = auto()
InTriOut = auto()
class IOType(Enum):
In = auto()
Out = auto()
TriOut = auto()
InTriOut = auto()
+
class IOConn(Record):
lengths = {
IOType.In: 1,
class IOConn(Record):
lengths = {
IOType.In: 1,
@@
-208,6
+211,7
@@
class IOConn(Record):
self._iotype = iotype
self._iotype = iotype
+
class _IDBypassBlock(Elaboratable):
"""TAP subblock for the ID shift register"""
def __init__(self, *, manufacturer_id, part_number, version,
class _IDBypassBlock(Elaboratable):
"""TAP subblock for the ID shift register"""
def __init__(self, *, manufacturer_id, part_number, version,
@@
-306,6
+310,7
@@
class ShiftReg(Record):
]
super().__init__(layout, name=name, src_loc_at=src_loc_at+1)
]
super().__init__(layout, name=name, src_loc_at=src_loc_at+1)
+
class TAP(Elaboratable):
#TODO: Document TAP
def __init__(self, *, with_reset=False, ir_width=None,
class TAP(Elaboratable):
#TODO: Document TAP
def __init__(self, *, with_reset=False, ir_width=None,