(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 3eda8f6cca4e36bf6427cbff04a28169fb73814f..2907b908c974b1ed1269905bc28f97e5347e5dd6 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -100,7 +100,8 @@ this is the case.
 
 Many Vector ISAs allow interrupts to occur in the middle of
 processing of large Vector operations, only under the condition
 
 Many Vector ISAs allow interrupts to occur in the middle of
 processing of large Vector operations, only under the condition

-that continuation on return will restart the entire operation.
+that partial results are cleanly discarded, and continuation on return
+from the Trap Handler will restart the entire operation.

 The reason is that saving of full Architectural State is
 not practical.
 
 The reason is that saving of full Architectural State is
 not practical.
 


@@ -113,8 +114,11 @@ at all times
 throughout
 this Chapter).
 *Any* element is Interruptible and Simple-V has
 throughout
 this Chapter).
 *Any* element is Interruptible and Simple-V has

-been carefully designed to ensure that Architectural State may
-be fully preserved regardless of that same State.
+been carefully designed to guarantee that Architectural State may
+be fully preserved and restored regardless of that same State, but
+it is not necessarily guaranteed that the amount of time needed to recover
+will be low latency (particularly if REMAP
+is active).

 
 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
 but the full SVP64 Architectural State may be saved and
 
 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
 but the full SVP64 Architectural State may be saved and