- self.assertEqual([repr(v) for v in fn.ops], [
- "Op(kind=OpKind.FuncArgR3, "
- "input_vals=[], "
- "input_uses=(), immediates=[], "
- "outputs=(<ptr_in.outputs[0]: <I64>>,), "
- "name='ptr_in')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[3], "
- "outputs=(<lhs_setvl.outputs[0]: <VL_MAXVL>>,), "
- "name='lhs_setvl')",
- "Op(kind=OpKind.SvLd, "
- "input_vals=[<ptr_in.outputs[0]: <I64>>, "
- "<lhs_setvl.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<load_lhs.input_uses[0]: <I64>>, "
- "<load_lhs.input_uses[1]: <VL_MAXVL>>), immediates=[48], "
- "outputs=(<load_lhs.outputs[0]: <I64*3>>,), "
- "name='load_lhs')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[3], "
- "outputs=(<rhs_setvl.outputs[0]: <VL_MAXVL>>,), "
- "name='rhs_setvl')",
- "Op(kind=OpKind.SvLd, "
- "input_vals=[<ptr_in.outputs[0]: <I64>>, "
- "<rhs_setvl.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<load_rhs.input_uses[0]: <I64>>, "
- "<load_rhs.input_uses[1]: <VL_MAXVL>>), immediates=[72], "
- "outputs=(<load_rhs.outputs[0]: <I64*3>>,), "
- "name='load_rhs')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[3], "
- "outputs=(<rhs_setvl2.outputs[0]: <VL_MAXVL>>,), "
- "name='rhs_setvl2')",
- "Op(kind=OpKind.Spread, "
- "input_vals=[<load_rhs.outputs[0]: <I64*3>>, "
- "<rhs_setvl2.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<rhs_spread.input_uses[0]: <I64*3>>, "
- "<rhs_spread.input_uses[1]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<rhs_spread.outputs[0]: <I64>>, "
- "<rhs_spread.outputs[1]: <I64>>, "
- "<rhs_spread.outputs[2]: <I64>>), "
- "name='rhs_spread')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[3], "
- "outputs=(<lhs_setvl3.outputs[0]: <VL_MAXVL>>,), "
- "name='lhs_setvl3')",
- "Op(kind=OpKind.LI, "
- "input_vals=[], "
- "input_uses=(), immediates=[0], "
- "outputs=(<zero.outputs[0]: <I64>>,), "
- "name='zero')",
- "Op(kind=OpKind.SvMAddEDU, "
- "input_vals=[<load_lhs.outputs[0]: <I64*3>>, "
- "<rhs_spread.outputs[0]: <I64>>, "
- "<zero.outputs[0]: <I64>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<mul0.input_uses[0]: <I64*3>>, "
- "<mul0.input_uses[1]: <I64>>, "
- "<mul0.input_uses[2]: <I64>>, "
- "<mul0.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<mul0.outputs[0]: <I64*3>>, "
- "<mul0.outputs[1]: <I64>>), "
- "name='mul0')",
- "Op(kind=OpKind.Spread, "
- "input_vals=[<mul0.outputs[0]: <I64*3>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<mul0_rt_spread.input_uses[0]: <I64*3>>, "
- "<mul0_rt_spread.input_uses[1]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<mul0_rt_spread.outputs[0]: <I64>>, "
- "<mul0_rt_spread.outputs[1]: <I64>>, "
- "<mul0_rt_spread.outputs[2]: <I64>>), "
- "name='mul0_rt_spread')",
- "Op(kind=OpKind.SvMAddEDU, "
- "input_vals=[<load_lhs.outputs[0]: <I64*3>>, "
- "<rhs_spread.outputs[1]: <I64>>, "
- "<zero.outputs[0]: <I64>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<mul1.input_uses[0]: <I64*3>>, "
- "<mul1.input_uses[1]: <I64>>, "
- "<mul1.input_uses[2]: <I64>>, "
- "<mul1.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<mul1.outputs[0]: <I64*3>>, "
- "<mul1.outputs[1]: <I64>>), "
- "name='mul1')",
- "Op(kind=OpKind.Concat, "
- "input_vals=[<mul0_rt_spread.outputs[1]: <I64>>, "
- "<mul0_rt_spread.outputs[2]: <I64>>, "
- "<mul0.outputs[1]: <I64>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add1_rb_concat.input_uses[0]: <I64>>, "
- "<add1_rb_concat.input_uses[1]: <I64>>, "
- "<add1_rb_concat.input_uses[2]: <I64>>, "
- "<add1_rb_concat.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add1_rb_concat.outputs[0]: <I64*3>>,), "
- "name='add1_rb_concat')",
- "Op(kind=OpKind.ClearCA, "
- "input_vals=[], "
- "input_uses=(), immediates=[], "
- "outputs=(<clear_ca1.outputs[0]: <CA>>,), "
- "name='clear_ca1')",
- "Op(kind=OpKind.SvAddE, "
- "input_vals=[<mul1.outputs[0]: <I64*3>>, "
- "<add1_rb_concat.outputs[0]: <I64*3>>, "
- "<clear_ca1.outputs[0]: <CA>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add1.input_uses[0]: <I64*3>>, "
- "<add1.input_uses[1]: <I64*3>>, "
- "<add1.input_uses[2]: <CA>>, "
- "<add1.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add1.outputs[0]: <I64*3>>, "
- "<add1.outputs[1]: <CA>>), "
- "name='add1')",
- "Op(kind=OpKind.Spread, "
- "input_vals=[<add1.outputs[0]: <I64*3>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add1_rt_spread.input_uses[0]: <I64*3>>, "
- "<add1_rt_spread.input_uses[1]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add1_rt_spread.outputs[0]: <I64>>, "
- "<add1_rt_spread.outputs[1]: <I64>>, "
- "<add1_rt_spread.outputs[2]: <I64>>), "
- "name='add1_rt_spread')",
- "Op(kind=OpKind.AddZE, "
- "input_vals=[<mul1.outputs[1]: <I64>>, "
- "<add1.outputs[1]: <CA>>], "
- "input_uses=(<add_hi1.input_uses[0]: <I64>>, "
- "<add_hi1.input_uses[1]: <CA>>), immediates=[], "
- "outputs=(<add_hi1.outputs[0]: <I64>>, "
- "<add_hi1.outputs[1]: <CA>>), "
- "name='add_hi1')",
- "Op(kind=OpKind.SvMAddEDU, "
- "input_vals=[<load_lhs.outputs[0]: <I64*3>>, "
- "<rhs_spread.outputs[2]: <I64>>, "
- "<zero.outputs[0]: <I64>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<mul2.input_uses[0]: <I64*3>>, "
- "<mul2.input_uses[1]: <I64>>, "
- "<mul2.input_uses[2]: <I64>>, "
- "<mul2.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<mul2.outputs[0]: <I64*3>>, "
- "<mul2.outputs[1]: <I64>>), "
- "name='mul2')",
- "Op(kind=OpKind.Concat, "
- "input_vals=[<add1_rt_spread.outputs[1]: <I64>>, "
- "<add1_rt_spread.outputs[2]: <I64>>, "
- "<add_hi1.outputs[0]: <I64>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add2_rb_concat.input_uses[0]: <I64>>, "
- "<add2_rb_concat.input_uses[1]: <I64>>, "
- "<add2_rb_concat.input_uses[2]: <I64>>, "
- "<add2_rb_concat.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add2_rb_concat.outputs[0]: <I64*3>>,), "
- "name='add2_rb_concat')",
- "Op(kind=OpKind.ClearCA, "
- "input_vals=[], "
- "input_uses=(), immediates=[], "
- "outputs=(<clear_ca2.outputs[0]: <CA>>,), "
- "name='clear_ca2')",
- "Op(kind=OpKind.SvAddE, "
- "input_vals=[<mul2.outputs[0]: <I64*3>>, "
- "<add2_rb_concat.outputs[0]: <I64*3>>, "
- "<clear_ca2.outputs[0]: <CA>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add2.input_uses[0]: <I64*3>>, "
- "<add2.input_uses[1]: <I64*3>>, "
- "<add2.input_uses[2]: <CA>>, "
- "<add2.input_uses[3]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add2.outputs[0]: <I64*3>>, "
- "<add2.outputs[1]: <CA>>), "
- "name='add2')",
- "Op(kind=OpKind.Spread, "
- "input_vals=[<add2.outputs[0]: <I64*3>>, "
- "<lhs_setvl3.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<add2_rt_spread.input_uses[0]: <I64*3>>, "
- "<add2_rt_spread.input_uses[1]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<add2_rt_spread.outputs[0]: <I64>>, "
- "<add2_rt_spread.outputs[1]: <I64>>, "
- "<add2_rt_spread.outputs[2]: <I64>>), "
- "name='add2_rt_spread')",
- "Op(kind=OpKind.AddZE, "
- "input_vals=[<mul2.outputs[1]: <I64>>, "
- "<add2.outputs[1]: <CA>>], "
- "input_uses=(<add_hi2.input_uses[0]: <I64>>, "
- "<add_hi2.input_uses[1]: <CA>>), immediates=[], "
- "outputs=(<add_hi2.outputs[0]: <I64>>, "
- "<add_hi2.outputs[1]: <CA>>), "
- "name='add_hi2')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[6], "
- "outputs=(<retval_setvl.outputs[0]: <VL_MAXVL>>,), "
- "name='retval_setvl')",
- "Op(kind=OpKind.Concat, "
- "input_vals=[<mul0_rt_spread.outputs[0]: <I64>>, "
- "<add1_rt_spread.outputs[0]: <I64>>, "
- "<add2_rt_spread.outputs[0]: <I64>>, "
- "<add2_rt_spread.outputs[1]: <I64>>, "
- "<add2_rt_spread.outputs[2]: <I64>>, "
- "<add_hi2.outputs[0]: <I64>>, "
- "<retval_setvl.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<concat_retval.input_uses[0]: <I64>>, "
- "<concat_retval.input_uses[1]: <I64>>, "
- "<concat_retval.input_uses[2]: <I64>>, "
- "<concat_retval.input_uses[3]: <I64>>, "
- "<concat_retval.input_uses[4]: <I64>>, "
- "<concat_retval.input_uses[5]: <I64>>, "
- "<concat_retval.input_uses[6]: <VL_MAXVL>>), immediates=[], "
- "outputs=(<concat_retval.outputs[0]: <I64*6>>,), "
- "name='concat_retval')",
- "Op(kind=OpKind.SetVLI, "
- "input_vals=[], "
- "input_uses=(), immediates=[6], "
- "outputs=(<dest_setvl.outputs[0]: <VL_MAXVL>>,), "
- "name='dest_setvl')",
- "Op(kind=OpKind.SvStd, "
- "input_vals=[<concat_retval.outputs[0]: <I64*6>>, "
- "<ptr_in.outputs[0]: <I64>>, "
- "<dest_setvl.outputs[0]: <VL_MAXVL>>], "
- "input_uses=(<store_dest.input_uses[0]: <I64*6>>, "
- "<store_dest.input_uses[1]: <I64>>, "
- "<store_dest.input_uses[2]: <VL_MAXVL>>), immediates=[0], "
- "outputs=(), "
- "name='store_dest')",
- ])
+ self.assertEqual(
+ fn.ops_to_str(),
+ "ptr_in:\n"
+ " (<...outputs[0]: <I64>>) <= FuncArgR3\n"
+ "lhs_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x3)\n"
+ "load_lhs:\n"
+ " (<...outputs[0]: <I64*3>>) <= SvLd(\n"
+ " <ptr_in.outputs[0]: <I64>>,\n"
+ " <lhs_setvl.outputs[0]: <VL_MAXVL>>, 0x30)\n"
+ "rhs_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x3)\n"
+ "load_rhs:\n"
+ " (<...outputs[0]: <I64*3>>) <= SvLd(\n"
+ " <ptr_in.outputs[0]: <I64>>,\n"
+ " <rhs_setvl.outputs[0]: <VL_MAXVL>>, 0x48)\n"
+ "mul_rhs_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x3)\n"
+ "mul_rhs_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>) <= Spread(\n"
+ " <load_rhs.outputs[0]: <I64*3>>,\n"
+ " <mul_rhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_zero:\n"
+ " (<...outputs[0]: <I64>>) <= LI(0x0)\n"
+ "mul_lhs_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x3)\n"
+ "mul_zero2:\n"
+ " (<...outputs[0]: <I64>>) <= LI(0x0)\n"
+ "mul_0_mul:\n"
+ " (<...outputs[0]: <I64*3>>, <...outputs[1]: <I64>>\n"
+ " ) <= SvMAddEDU(<load_lhs.outputs[0]: <I64*3>>,\n"
+ " <mul_rhs_spread.outputs[0]: <I64>>,\n"
+ " <mul_zero.outputs[0]: <I64>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_0_mul_rt_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>) <= Spread(\n"
+ " <mul_0_mul.outputs[0]: <I64*3>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_mul:\n"
+ " (<...outputs[0]: <I64*3>>, <...outputs[1]: <I64>>\n"
+ " ) <= SvMAddEDU(<load_lhs.outputs[0]: <I64*3>>,\n"
+ " <mul_rhs_spread.outputs[1]: <I64>>,\n"
+ " <mul_zero.outputs[0]: <I64>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_mul_rt_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>) <= Spread(\n"
+ " <mul_1_mul.outputs[0]: <I64*3>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_cast_retval_zero:\n"
+ " (<...outputs[0]: <I64>>) <= LI(0x0)\n"
+ "mul_1_cast_pp_zero:\n"
+ " (<...outputs[0]: <I64>>) <= LI(0x0)\n"
+ "mul_1_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x5)\n"
+ "mul_1_retval_concat:\n"
+ " (<...outputs[0]: <I64*5>>) <= Concat(\n"
+ " <mul_0_mul_rt_spread.outputs[1]: <I64>>,\n"
+ " <mul_0_mul_rt_spread.outputs[2]: <I64>>,\n"
+ " <mul_0_mul.outputs[1]: <I64>>,\n"
+ " <mul_1_cast_retval_zero.outputs[0]: <I64>>,\n"
+ " <mul_1_cast_retval_zero.outputs[0]: <I64>>,\n"
+ " <mul_1_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_pp_concat:\n"
+ " (<...outputs[0]: <I64*5>>) <= Concat(\n"
+ " <mul_1_mul_rt_spread.outputs[0]: <I64>>,\n"
+ " <mul_1_mul_rt_spread.outputs[1]: <I64>>,\n"
+ " <mul_1_mul_rt_spread.outputs[2]: <I64>>,\n"
+ " <mul_1_mul.outputs[1]: <I64>>,\n"
+ " <mul_1_cast_pp_zero.outputs[0]: <I64>>,\n"
+ " <mul_1_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_clear_ca:\n"
+ " (<...outputs[0]: <CA>>) <= ClearCA\n"
+ "mul_1_add:\n"
+ " (<...outputs[0]: <I64*5>>, <...outputs[1]: <CA>>\n"
+ " ) <= SvAddE(<mul_1_retval_concat.outputs[0]: <I64*5>>,\n"
+ " <mul_1_pp_concat.outputs[0]: <I64*5>>,\n"
+ " <mul_1_clear_ca.outputs[0]: <CA>>,\n"
+ " <mul_1_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_1_sum_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>, <...outputs[3]: <I64>>,\n"
+ " <...outputs[4]: <I64>>) <= Spread(\n"
+ " <mul_1_add.outputs[0]: <I64*5>>,\n"
+ " <mul_1_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_mul:\n"
+ " (<...outputs[0]: <I64*3>>, <...outputs[1]: <I64>>\n"
+ " ) <= SvMAddEDU(<load_lhs.outputs[0]: <I64*3>>,\n"
+ " <mul_rhs_spread.outputs[2]: <I64>>,\n"
+ " <mul_zero.outputs[0]: <I64>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_mul_rt_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>) <= Spread(\n"
+ " <mul_2_mul.outputs[0]: <I64*3>>,\n"
+ " <mul_lhs_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x4)\n"
+ "mul_2_retval_concat:\n"
+ " (<...outputs[0]: <I64*4>>) <= Concat(\n"
+ " <mul_1_sum_spread.outputs[1]: <I64>>,\n"
+ " <mul_1_sum_spread.outputs[2]: <I64>>,\n"
+ " <mul_1_sum_spread.outputs[3]: <I64>>,\n"
+ " <mul_1_sum_spread.outputs[4]: <I64>>,\n"
+ " <mul_2_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_pp_concat:\n"
+ " (<...outputs[0]: <I64*4>>) <= Concat(\n"
+ " <mul_2_mul_rt_spread.outputs[0]: <I64>>,\n"
+ " <mul_2_mul_rt_spread.outputs[1]: <I64>>,\n"
+ " <mul_2_mul_rt_spread.outputs[2]: <I64>>,\n"
+ " <mul_2_mul.outputs[1]: <I64>>,\n"
+ " <mul_2_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_clear_ca:\n"
+ " (<...outputs[0]: <CA>>) <= ClearCA\n"
+ "mul_2_add:\n"
+ " (<...outputs[0]: <I64*4>>, <...outputs[1]: <CA>>\n"
+ " ) <= SvAddE(<mul_2_retval_concat.outputs[0]: <I64*4>>,\n"
+ " <mul_2_pp_concat.outputs[0]: <I64*4>>,\n"
+ " <mul_2_clear_ca.outputs[0]: <CA>>,\n"
+ " <mul_2_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_2_sum_spread:\n"
+ " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
+ " <...outputs[2]: <I64>>, <...outputs[3]: <I64>>) <= Spread(\n"
+ " <mul_2_add.outputs[0]: <I64*4>>,\n"
+ " <mul_2_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "mul_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x6)\n"
+ "mul_concat:\n"
+ " (<...outputs[0]: <I64*6>>) <= Concat(\n"
+ " <mul_0_mul_rt_spread.outputs[0]: <I64>>,\n"
+ " <mul_1_sum_spread.outputs[0]: <I64>>,\n"
+ " <mul_2_sum_spread.outputs[0]: <I64>>,\n"
+ " <mul_2_sum_spread.outputs[1]: <I64>>,\n"
+ " <mul_2_sum_spread.outputs[2]: <I64>>,\n"
+ " <mul_2_sum_spread.outputs[3]: <I64>>,\n"
+ " <mul_setvl.outputs[0]: <VL_MAXVL>>)\n"
+ "dest_setvl:\n"
+ " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x6)\n"
+ "store_dest:\n"
+ " SvStd(<mul_concat.outputs[0]: <I64*6>>,\n"
+ " <ptr_in.outputs[0]: <I64>>,\n"
+ " <dest_setvl.outputs[0]: <VL_MAXVL>>, 0x0)"
+ )