+class DepCell(Elaboratable):
+ """ FU Dependency Cell
+ """
+ def __init__(self):
+ # inputs
+ self.pend_i = Signal(reset_less=True) # pending bit in (left)
+ self.issue_i = Signal(reset_less=True) # Issue in (top)
+ self.go_i = Signal(reset_less=True) # Go read/write in (left)
+
+ # wait
+ self.wait_o = Signal(reset_less=True) # wait out (right)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.l = l = SRLatch(sync=False) # async latch
+
+ # record current version of q in a sync'd register
+ cq = Signal() # resets to 0
+ m.d.sync += cq.eq(l.q)
+
+ # reset on go HI, set on dest and issue
+ m.d.comb += l.s.eq(self.issue_i & self.pend_i)
+ m.d.comb += l.r.eq(self.go_i)
+
+ # wait out
+ m.d.comb += self.wait_o.eq((cq | l.q) & ~self.issue_i)
+
+ return m
+
+ def __iter__(self):
+ yield self.pend_i
+ yield self.issue_i
+ yield self.go_i
+ yield self.wait_o
+
+ def ports(self):
+ return list(self)
+