+ # sigh have to do setvl here manually for now...
+ if opcode in ["setvl", "setvl."]:
+ insn = 22 << (31-5) # opcode 22, bits 0-5
+ fields = list(map(int, fields))
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= fields[1] << (31-15) # RA , bits 11-15
+ insn |= fields[2] << (31-23) # SVi , bits 16-23
+ insn |= fields[3] << (31-24) # vs , bit 24
+ insn |= fields[4] << (31-25) # ms , bit 25
+ insn |= 0b00000 << (31-30) # XO , bits 26..30
+ if opcode == 'setvl.':
+ insn |= 1 << (31-31) # Rc=1 , bit 31
+ print ("setvl", bin(insn))
+ yield ".long 0x%x" % insn
+ continue
+