first: SPR pipeline already has fast1 read/write
second: a new DecodeStateIn/Out object would be needed
instead just add FastRegs.DEC/TB to DecodeA/Out
third: there is probably a third somewhere
with m.Case(SPR.XER.value):
comb += self.fast_out.data.eq(FastRegs.XER)
comb += self.fast_out.ok.eq(1)
with m.Case(SPR.XER.value):
comb += self.fast_out.data.eq(FastRegs.XER)
comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.DEC.value):
+ comb += self.fast_out.data.eq(FastRegs.DEC)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.TB.value):
+ comb += self.fast_out.data.eq(FastRegs.TB)
+ comb += self.fast_out.ok.eq(1)
# : map to internal SPR numbers
# XXX TODO: dec and tb not to go through mapping.
with m.Default():
# : map to internal SPR numbers
# XXX TODO: dec and tb not to go through mapping.
with m.Default():
with m.Case(SPR.XER.value):
comb += self.fast_out.data.eq(FastRegs.XER)
comb += self.fast_out.ok.eq(1)
with m.Case(SPR.XER.value):
comb += self.fast_out.data.eq(FastRegs.XER)
comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.TB.value):
+ comb += self.fast_out.data.eq(FastRegs.TB)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.DEC.value):
+ comb += self.fast_out.data.eq(FastRegs.DEC)
+ comb += self.fast_out.ok.eq(1)
# : map to internal SPR numbers
# XXX TODO: dec and tb not to go through mapping.
with m.Default():
# : map to internal SPR numbers
# XXX TODO: dec and tb not to go through mapping.
with m.Default():
if regfile == 'STATE':
# STATE register numbering is *unary* encoded
PC = 1<<StateRegs.PC
if regfile == 'STATE':
# STATE register numbering is *unary* encoded
PC = 1<<StateRegs.PC
if name in ['cia', 'nia']:
return Const(1), PC # TODO: detect read-conditions
if name == 'msr':
if name in ['cia', 'nia']:
return Const(1), PC # TODO: detect read-conditions
if name == 'msr':
so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
- state_i, state_o = self.i.state, self.o.state
# take copy of D-Form TO field
x_fields = self.fields.FormXFX
# take copy of D-Form TO field
x_fields = self.fields.FormXFX
with m.Switch(spr):
# fast SPRs first
with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
with m.Switch(spr):
# fast SPRs first
with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
+ SPR.SRR1, SPR.XER, SPR.DEC):
comb += fast1_o.data.eq(a_i)
comb += fast1_o.ok.eq(1)
# XER is constructed
comb += fast1_o.data.eq(a_i)
comb += fast1_o.ok.eq(1)
# XER is constructed
comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
comb += ca_o.ok.eq(1)
comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
comb += ca_o.ok.eq(1)
- # STATE SPRs (dec, tb)
- with m.Case(SPR.DEC):
- comb += state_o.data.eq(a_i)
- comb += state_o.ok.eq(1)
with m.Switch(spr):
# fast SPRs first
with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
with m.Switch(spr):
# fast SPRs first
with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
+ SPR.XER, SPR.DEC, SPR.TB):
comb += o.data.eq(fast1_i)
with m.If(spr == SPR.XER):
# bits 0:31 and 35:43 are treated as reserved
comb += o.data.eq(fast1_i)
with m.If(spr == SPR.XER):
# bits 0:31 and 35:43 are treated as reserved
# carry
comb += o[63-XER_bits['CA']].eq(ca_i[0])
comb += o[63-XER_bits['CA32']].eq(ca_i[1])
# carry
comb += o[63-XER_bits['CA']].eq(ca_i[0])
comb += o[63-XER_bits['CA32']].eq(ca_i[1])
- # STATE SPRs (dec, tb)
- with m.Case(SPR.DEC, SPR.TB):
- comb += o.data.eq(state_i)
- comb += o.data[0:32].eq(state_i[32:64])
+ comb += o.data[0:32].eq(fast1_i[32:64])
regspec = [('INT', 'ra', '0:63'), # RA
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
regspec = [('INT', 'ra', '0:63'), # RA
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
- ('STATE', 'state', '0:63'), # SPR (state: DEC, TB)
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
regspec = [('INT', 'o', '0:63'), # RT
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
regspec = [('INT', 'o', '0:63'), # RT
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
- ('STATE', 'state', '0:63'), # SPR (state: DEC, TB)
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
('XER', 'xer_so', '32'), # XER bit 32: SO
('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
State regfile - PC, MSR, DEC, TB and later SimpleV VL
* QTY 4of 64-bit registers
State regfile - PC, MSR, DEC, TB and later SimpleV VL
* QTY 4of 64-bit registers
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
will probably have to also add one so it can get at the MSR as well.
(d_rd2)
will probably have to also add one so it can get at the MSR as well.
(d_rd2)
- Note: r/w state are used by SPR for MTSPR / MFSPR.
- Note: r/w issue are used by issuer to increment/decrement TB/DEC.
def __init__(self):
super().__init__(64, 4)
self.w_ports = {'nia': self.write_port("nia"),
'msr': self.write_port("msr"),
def __init__(self):
super().__init__(64, 4)
self.w_ports = {'nia': self.write_port("nia"),
'msr': self.write_port("msr"),
- 'state': self.read_port("state"), # writing DEC/TB
- 'issue': self.read_port("issue"), # writing DEC/TB
'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
'msr': self.read_port("msr"), # reading MSR (issuer)
'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
'msr': self.read_port("msr"), # reading MSR (issuer)
- 'state': self.read_port("state"), # reading DEC/TB
- 'issue': self.read_port("issue"), # reading DEC/TB
class FastRegs(RegFileMem): #RegFileArray):
"""FastRegs
class FastRegs(RegFileMem): #RegFileArray):
"""FastRegs
- FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER
+ FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
* QTY 6of 64-bit registers
* QTY 6of 64-bit registers
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
+
+ Note: r/w issue are used by issuer to increment/decrement TB/DEC.
SRR0 = 3
SRR1 = 4
XER = 5 # non-XER bits
SRR0 = 3
SRR1 = 4
XER = 5 # non-XER bits
- super().__init__(64, 6)
+ super().__init__(64, 8)
self.w_ports = {'fast1': self.write_port("dest1"),
self.w_ports = {'fast1': self.write_port("dest1"),
+ 'issue': self.write_port("issue"), # writing DEC/TB
}
self.r_ports = {'fast1': self.read_port("src1"),
'fast2': self.read_port("src2"),
}
self.r_ports = {'fast1': self.read_port("src1"),
'fast2': self.read_port("src2"),
+ 'issue': self.read_port("issue"), # reading DEC/TB