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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 10 Jun 2020 23:48:01 +0000
(
00:48
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 10 Jun 2020 23:48:01 +0000
(
00:48
+0100)
src/soc/decoder/power_regspec_map.py
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|
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|
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src/soc/experiment/compldst_multi.py
patch
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|
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src/soc/fu/compunits/test/test_compunit.py
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|
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src/soc/fu/ldst/test/test_pipe_caller.py
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src/soc/simulator/test_sim.py
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diff --git
a/src/soc/decoder/power_regspec_map.py
b/src/soc/decoder/power_regspec_map.py
index fdc9c323f11e1edad09c486e73a5a4f5cc04f0cb..a88375d0dcc1d02ffec2df6b855a4eedc9b9fa94 100644
(file)
--- a/
src/soc/decoder/power_regspec_map.py
+++ b/
src/soc/decoder/power_regspec_map.py
@@
-16,7
+16,8
@@
name, return a tuple of:
Note that some of the port numbering encoding is *unary*. in the case
of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
This actually matches directly with the XFX field in MTCR, and at
Note that some of the port numbering encoding is *unary*. in the case
of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
This actually matches directly with the XFX field in MTCR, and at
-some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO).
+some point that 8-bit mask from the instruction could actually be passed
+directly through to full_cr (TODO).
For the INT and CR numbering, these are expressed in binary in the
instruction (note however that XFX in MTCR is unary-masked!)
For the INT and CR numbering, these are expressed in binary in the
instruction (note however that XFX in MTCR is unary-masked!)
diff --git
a/src/soc/experiment/compldst_multi.py
b/src/soc/experiment/compldst_multi.py
index 851bc858f6ff09dcef867a6faf4338994f9c094b..630dc9b8984a7829bfa762b8c27d2c23277e6844 100644
(file)
--- a/
src/soc/experiment/compldst_multi.py
+++ b/
src/soc/experiment/compldst_multi.py
@@
-330,7
+330,7
@@
class LDSTCompUnit(RegSpecAPI, Elaboratable):
# dest operand latch
comb += wri_l.s.eq(issue_i)
# dest operand latch
comb += wri_l.s.eq(issue_i)
- sync += wri_l.r.eq(reset_w)
+ sync += wri_l.r.eq(reset_w
| Repl(self.done_o, self.n_dst)
)
# update-mode operand latch (EA written to reg 2)
sync += upd_l.s.eq(reset_i)
# update-mode operand latch (EA written to reg 2)
sync += upd_l.s.eq(reset_i)
@@
-338,7
+338,7
@@
class LDSTCompUnit(RegSpecAPI, Elaboratable):
# store latch
comb += sto_l.s.eq(addr_ok & op_is_st)
# store latch
comb += sto_l.s.eq(addr_ok & op_is_st)
-
comb
+= sto_l.r.eq(reset_s)
+
sync
+= sto_l.r.eq(reset_s)
# reset latch
comb += rst_l.s.eq(addr_ok) # start when address is ready
# reset latch
comb += rst_l.s.eq(addr_ok) # start when address is ready
@@
-413,15
+413,15
@@
class LDSTCompUnit(RegSpecAPI, Elaboratable):
comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
# address release only if addr ready, but Port must be idle
comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
# address release only if addr ready, but Port must be idle
- comb += self.adr_rel_o.eq(adr_l.q & busy_o)
+ comb += self.adr_rel_o.eq(a
lu_valid & a
dr_l.q & busy_o)
# store release when st ready *and* all operands read (and no shadow)
comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
self.shadown_i)
# request write of LD result. waits until shadow is dropped.
# store release when st ready *and* all operands read (and no shadow)
comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
self.shadown_i)
# request write of LD result. waits until shadow is dropped.
- comb += self.wr.rel[0].eq(
wri_l.q & busy_o & lod_l.qn & op_is_ld
&
- self.shadown_i)
+ comb += self.wr.rel[0].eq(
rd_done & wri_l.q & busy_o & lod_l.qn
&
+
op_is_ld &
self.shadown_i)
# request write of EA result only in update mode
comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
# request write of EA result only in update mode
comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
diff --git
a/src/soc/fu/compunits/test/test_compunit.py
b/src/soc/fu/compunits/test/test_compunit.py
index 971e46a8b0ea8f7a2ddc1ccfd6d3dfbc02d45061..a62a469480faa2f09dbab0e87c6db70cbe52ee8e 100644
(file)
--- a/
src/soc/fu/compunits/test/test_compunit.py
+++ b/
src/soc/fu/compunits/test/test_compunit.py
@@
-56,6
+56,7
@@
def get_cu_output(cu, idx, code):
yield
yield cu.wr.go[idx].eq(0)
print ("result", repr(code), idx, wrop, wrok, hex(result))
yield
yield cu.wr.go[idx].eq(0)
print ("result", repr(code), idx, wrop, wrok, hex(result))
+
return result
return result
@@
-198,12
+199,12
@@
class TestRunner(FHDLTestCase):
wr_rel_o = yield cu.wr.rel
print ("before inputs, rd_rel, wr_rel: ",
bin(rd_rel_o), bin(wr_rel_o))
wr_rel_o = yield cu.wr.rel
print ("before inputs, rd_rel, wr_rel: ",
bin(rd_rel_o), bin(wr_rel_o))
+ yield
assert wr_rel_o == 0, "wr.rel %s must be zero. "\
"previous instr not written all regs\n"\
"respec %s" % \
(bin(wr_rel_o), cu.rwid[1])
yield from set_cu_inputs(cu, inp)
assert wr_rel_o == 0, "wr.rel %s must be zero. "\
"previous instr not written all regs\n"\
"respec %s" % \
(bin(wr_rel_o), cu.rwid[1])
yield from set_cu_inputs(cu, inp)
- yield
rd_rel_o = yield cu.rd.rel
wr_rel_o = yield cu.wr.rel
wrmask = yield cu.wrmask
rd_rel_o = yield cu.rd.rel
wr_rel_o = yield cu.wr.rel
wrmask = yield cu.wrmask
@@
-219,6
+220,14
@@
class TestRunner(FHDLTestCase):
# get all outputs (one by one, just "because")
res = yield from get_cu_outputs(cu, code)
# get all outputs (one by one, just "because")
res = yield from get_cu_outputs(cu, code)
+ # wait for busy to go low
+ while True:
+ busy_o = yield cu.busy_o
+ print ("busy", busy_o)
+ if not busy_o:
+ break
+ yield
+
yield from self.iodef.check_cu_outputs(res, pdecode2,
sim, code)
yield from self.iodef.check_cu_outputs(res, pdecode2,
sim, code)
diff --git
a/src/soc/fu/ldst/test/test_pipe_caller.py
b/src/soc/fu/ldst/test/test_pipe_caller.py
index dccdaa8c5d7c8d4b6aa8f10062d681d86a471d29..692fc668f3e34d996bda737c1a5515f38b507170 100644
(file)
--- a/
src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/
src/soc/fu/ldst/test/test_pipe_caller.py
@@
-76,7
+76,7
@@
class LDSTTestCase(FHDLTestCase):
self.run_tst_program(Program(lst), initial_regs,
initial_mem=initial_mem)
self.run_tst_program(Program(lst), initial_regs,
initial_mem=initial_mem)
- def tst_2_load_store(self):
+ def t
e
st_2_load_store(self):
lst = ["stw 2, 0(1)",
"lwz 3, 0(1)"]
initial_regs = [0] * 32
lst = ["stw 2, 0(1)",
"lwz 3, 0(1)"]
initial_regs = [0] * 32
diff --git
a/src/soc/simulator/test_sim.py
b/src/soc/simulator/test_sim.py
index 9d00476d6379fdce714bbc888319a9d5301f4348..fbe792b556d5a28e0afa647c6f24924adfb103fb 100644
(file)
--- a/
src/soc/simulator/test_sim.py
+++ b/
src/soc/simulator/test_sim.py
@@
-159,7
+159,7
@@
class DecoderTestCase(FHDLTestCase):
print("qemu pc", hex(qpc))
print("qemu cr", hex(qcr))
print("qemu xer", bin(qxer))
print("qemu pc", hex(qpc))
print("qemu cr", hex(qcr))
print("qemu xer", bin(qxer))
- print("sim pc",
sim.pc.CIA.value
)
+ print("sim pc",
hex(sim.pc.CIA.value)
)
print("sim cr", hex(sim_cr))
print("sim xer", hex(sim_xer))
self.assertEqual(qcr, sim_cr)
print("sim cr", hex(sim_cr))
print("sim xer", hex(sim_xer))
self.assertEqual(qcr, sim_cr)