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Add ld and st instructions to the reg/reg test
author
Michael Nolan
<mtnolan2640@gmail.com>
Thu, 19 Mar 2020 18:35:01 +0000
(14:35 -0400)
committer
Michael Nolan
<mtnolan2640@gmail.com>
Thu, 19 Mar 2020 18:35:01 +0000
(14:35 -0400)
src/soc/decoder/test/test_decoder_gas.py
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diff --git
a/src/soc/decoder/test/test_decoder_gas.py
b/src/soc/decoder/test/test_decoder_gas.py
index 074e628fb89c1710038db74d65493c7bd9a5e9f2..9be815f5b44bb1cf85d012813a2ec20e434edcd5 100644
(file)
--- a/
src/soc/decoder/test/test_decoder_gas.py
+++ b/
src/soc/decoder/test/test_decoder_gas.py
@@
-28,6
+28,8
@@
class RegRegOp:
"and": InternalOp.OP_AND,
"or": InternalOp.OP_OR,
"add.": InternalOp.OP_ADD,
"and": InternalOp.OP_AND,
"or": InternalOp.OP_OR,
"add.": InternalOp.OP_ADD,
+ "lwzx": InternalOp.OP_LOAD,
+ "stwx": InternalOp.OP_STORE,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
@@
-43,7
+45,11
@@
class RegRegOp:
return string
def check_results(self, pdecode2):
return string
def check_results(self, pdecode2):
- r1sel = yield pdecode2.e.write_reg.data
+ if self.opcode == InternalOp.OP_STORE:
+ r1sel = yield pdecode2.e.read_reg3.data
+ else:
+ r1sel = yield pdecode2.e.write_reg.data
+
r3sel = yield pdecode2.e.read_reg2.data
# For some reason r2 gets decoded either in read_reg1
r3sel = yield pdecode2.e.read_reg2.data
# For some reason r2 gets decoded either in read_reg1