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correction in enable and selection lines for twi_scl
author
rishucoding
<rishucoding@gmail.com>
Wed, 4 Jul 2018 07:07:11 +0000
(12:37 +0530)
committer
rishucoding
<rishucoding@gmail.com>
Wed, 4 Jul 2018 07:07:11 +0000
(12:37 +0530)
src/test_bsv/tests/test_pinmux.py
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diff --git
a/src/test_bsv/tests/test_pinmux.py
b/src/test_bsv/tests/test_pinmux.py
index 16506848cbbb137c433b696d80a433383c3ce36e..3da87a69054981dbd01737612a8a49006b74c640 100644
(file)
--- a/
src/test_bsv/tests/test_pinmux.py
+++ b/
src/test_bsv/tests/test_pinmux.py
@@
-50,6
+50,7
@@
def pinmux_gpio2(dut):
str(dut.iocell_side_io2_cell_out))
# GPIO2-in test (first see if it's tri-state)
str(dut.iocell_side_io2_cell_out))
# GPIO2-in test (first see if it's tri-state)
+ #
if str(dut.peripheral_side_gpioa_a2_in) != "x":
raise TestFailure(
"gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
if str(dut.peripheral_side_gpioa_a2_in) != "x":
raise TestFailure(
"gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
@@
-128,12
+129,12
@@
def pinmux_twi_scl(dut):
# mux selection lines, each input two bit wide
dut.mux_lines_cell0_mux_in = 1
dut.mux_lines_cell1_mux_in = 2
# mux selection lines, each input two bit wide
dut.mux_lines_cell0_mux_in = 1
dut.mux_lines_cell1_mux_in = 2
- dut.mux_lines_cell2_mux_in =
0
+ dut.mux_lines_cell2_mux_in =
2
yield Timer(2)
# enable input for mux
dut.EN_mux_lines_cell0_mux = 0
yield Timer(2)
# enable input for mux
dut.EN_mux_lines_cell0_mux = 0
- dut.EN_mux_lines_cell1_mux =
1
- dut.EN_mux_lines_cell2_mux =
0
+ dut.EN_mux_lines_cell1_mux =
0
+ dut.EN_mux_lines_cell2_mux =
1
yield Timer(2)
yield Timer(2)