testcase refactoring

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 8f9f0df9e54debfa0c7525e84db1678fb240066c..3fac8cb649354b110779a250ee71935106065240 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -28,6 +28,8 @@ from soc.scoreboard.addr_match import LenExpand
 
 # for testing purposes
 from soc.experiment.testmem import TestMemory
+#from soc.scoreboard.addr_split import LDSTSplitter
+
 
 import unittest
 
@@ -338,43 +340,3 @@ class TestMemoryPortInterface(PortInterfaceBase):
     def ports(self):
         yield from super().ports()
         # TODO: memory ports
-
-class TestCachedMemoryPortInterface(PortInterfaceBase):
-    """TestCacheMemoryPortInterface
-
-    This is a test class for simple verification of LDSTSplitter
-    conforming to PortInterface,
-    """
-
-    def __init__(self, regwid=64, addrwid=4):
-        super().__init__(regwid, addrwid)
-        # hard-code memory addressing width to 6 bits
-        self.mem = None
-
-    def set_wr_addr(self, m, addr, mask):
-        lsbaddr, msbaddr = self.splitaddr(addr)
-        m.d.comb += self.mem.wrport.addr.eq(msbaddr)
-
-    def set_rd_addr(self, m, addr, mask):
-        lsbaddr, msbaddr = self.splitaddr(addr)
-        m.d.comb += self.mem.rdport.addr.eq(msbaddr)
-
-    def set_wr_data(self, m, data, wen):
-        m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
-        m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
-        return Const(1, 1)
-
-    def get_rd_data(self, m):
-        return self.mem.rdport.data, Const(1, 1)
-
-    def elaborate(self, platform):
-        m = super().elaborate(platform)
-
-        # add TestMemory as submodule
-        m.submodules.mem = self.mem
-
-        return m
-
-    def ports(self):
-        yield from super().ports()
-        # TODO: memory ports

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index ae1ae7e8872e1e4f427b21e16367526d08cb9961..3a17749f80963e5cccb31ca3f5ba46256f9593e9 100644 (file)
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -10,22 +10,49 @@ from soc.scoreboard.addr_match import LenExpand
 
 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
 
-#cxxsim = False
-#if cxxsim:
-#    from nmigen.sim.cxxsim import Simulator, Settle
-#else:
-#    from nmigen.back.pysim import Simulator, Settle
+from soc.experiment.pimem import PortInterfaceBase
+
 from nmigen.compat.sim import run_simulation, Settle
 
-def writeMulti(dut):
-    for i in range(dut.n_units):
-        yield dut.dports[i].is_st_i.eq(1)
-        yield dut.dports[i].addr.data.eq(i)
-    yield
-    # TODO assert that outputs are valid
+class TestCachedMemoryPortInterface(PortInterfaceBase):
+    """TestCacheMemoryPortInterface
+
+    This is a test class for simple verification of LDSTSplitter
+    conforming to PortInterface,
+    """
+
+    def __init__(self, regwid=64, addrwid=4):
+        super().__init__(regwid, addrwid)
+        #self.ldst = LDSTSplitter()
+
+    def set_wr_addr(self, m, addr, mask):
+        lsbaddr, msbaddr = self.splitaddr(addr)
+        #m.d.comb += self.mem.wrport.addr.eq(msbaddr)
+
+    def set_rd_addr(self, m, addr, mask):
+        lsbaddr, msbaddr = self.splitaddr(addr)
+        #m.d.comb += self.mem.rdport.addr.eq(msbaddr)
+
+    def set_wr_data(self, m, data, wen):
+        #m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
+        #m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
+        return Const(1, 1) #document return value
+
+    def get_rd_data(self, m):
+        #return self.mem.rdport.data, Const(1, 1)
+        return None 
 
-def test_cache_run(dut):
-    yield from writeMulti(dut)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        # add TestMemory as submodule
+        m.submodules.ldst = self.ldst
+
+        return m
+
+    def ports(self):
+        yield from super().ports()
+        # TODO: memory ports
 
 def test_cache_single_run(dut):
     #test single byte
@@ -33,23 +60,13 @@ def test_cache_single_run(dut):
     data = 0xfeedface
     yield from pi_st(dut.pi, addr, data, 1)
 
-def test_cache():
-    dut = L0CacheBuffer2()
-
-    #vl = rtlil.convert(dut, ports=dut.ports())
-    #with open("test_data_merger.il", "w") as f:
-    #    f.write(vl)
-
-    run_simulation(dut, test_cache_run(dut),
-                   vcd_name='test_cache.vcd')
-
 def test_cache_single():
-    dut = LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
+    dut = TestCachedMemoryPortInterface()
+    #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
 
     run_simulation(dut, test_cache_single_run(dut),
                    vcd_name='test_cache_single.vcd')
 
 
 if __name__ == '__main__':
-    #test_cache()
     test_cache_single()