whoops correct links

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index 1cecf298cf5ac3c3203315b23dc79a212953f87d..880db24e0584906f225c67f7d016a7c213453bb9 100644 (file)
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -12,13 +12,13 @@ All of these are entirely Libre-Licensed:
   OpenPOWER CPU with
   [[openpower/sv/bitmanip]] extensions
 * 180/130 nm (TBD)
-* 5x [[shakhti/m_class/RGMII]] Gigabit Ethernet PHYs
-* 2x USB [[shakhti/m_class/ULPI]] PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
+* 2x USB [[shakti/m_class/ULPI]] PHYs
 * Direct DMA interface (independent bulk transfer)
 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
 * On-board Dual-ported SRAM (for Packet Buffers)
-* Opencores [[shakhti/m_class/sdram]]
+* Opencores [[shakti/m_class/sdram]]
 * Wishbone interfaces to all peripherals
 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
   Interrupt Controller