(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 25cf68e572cc4b4262279947cbe953c8563dee74..5db0d7cbfa3388353d8ebbd3ed4bae3918a75e64 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -127,6 +127,10 @@ Examples of the former type:
   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
   of BF to be tested is identified.
 
+Just as with SVP64 [[sv/branches]] there is the option to truncate
+VL to include the element being tested (`VLi=1`) and to exclude it
+(`VLi=0`).
+
 # Predicate-result Condition Register operations
 
 These are again slightly different compared to SVP64 arithmetic