add beginnings of LDST compunit test

diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py
new file mode 100644 (file)
index 0000000..a223554
--- /dev/null
+++ b/src/soc/fu/compunits/test/test_ldst_compunit.py
@@ -0,0 +1,76 @@
+import unittest
+from soc.decoder.power_enums import (XER_bits, Function)
+
+from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase, get_cu_inputs
+
+from soc.fu.compunits.compunits import LDSTFunctionUnit
+from soc.fu.compunits.test.test_compunit import TestRunner
+
+
+class LDSTTestRunner(TestRunner):
+    def __init__(self, test_data):
+        super().__init__(test_data, LDSTFunctionUnit, self,
+                         Function.LOGICAL)
+
+    def get_cu_inputs(self, dec2, sim):
+        """naming (res) must conform to LDSTFunctionUnit input regspec
+        """
+        res = yield from get_cu_inputs(dec2, sim)
+        return res
+
+    def check_cu_outputs(self, res, dec2, sim, code):
+        """naming (res) must conform to LDSTFunctionUnit output regspec
+        """
+
+        # RT
+        out_reg_valid = yield dec2.e.write_reg.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_reg.data
+            expected = sim.gpr(write_reg_idx).value
+            cu_out = res['o']
+            print(f"expected {expected:x}, actual: {cu_out:x}")
+            self.assertEqual(expected, cu_out, code)
+
+        # RA
+        out_reg_valid = yield dec2.e.write_ea.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_ea.data
+            expected = sim.gpr(write_reg_idx).value
+            cu_out = res['o1']
+            print(f"expected {expected:x}, actual: {cu_out:x}")
+            self.assertEqual(expected, cu_out, code)
+
+        rc = yield dec2.e.rc.data
+        op = yield dec2.e.insn_type
+        cridx_ok = yield dec2.e.write_cr.ok
+        cridx = yield dec2.e.write_cr.data
+
+        print ("check extra output", repr(code), cridx_ok, cridx)
+
+        if rc:
+            self.assertEqual(cridx_ok, 1, code)
+            self.assertEqual(cridx, 0, code)
+
+        # CR (CR0-7)
+        if cridx_ok:
+            cr_expected = sim.crl[cridx].get_range().value
+            cr_actual = res['cr_a']
+            print ("CR", cridx, cr_expected, cr_actual)
+            self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+
+        # XER.so
+        return
+        oe = yield dec2.e.oe
+        if oe:
+            expected_so = 1 if sim.spr['XER'][XER_bits['so']] else 0
+            xer_so = res['xer_so']
+            self.assertEqual(expected_so, xer_so, code)
+
+
+if __name__ == "__main__":
+    unittest.main(exit=False)
+    suite = unittest.TestSuite()
+    suite.addTest(LDSTTestRunner(LDSTTestCase.test_data))
+
+    runner = unittest.TextTestRunner()
+    runner.run(suite)

diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
new file mode 100644 (file)
index 0000000..d34323b
--- /dev/null
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -0,0 +1,78 @@
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+from nmigen.cli import rtlil
+import unittest
+from soc.decoder.isa.caller import ISACaller, special_sprs
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.selectable_int import SelectableInt
+from soc.simulator.program import Program
+from soc.decoder.isa.all import ISA
+
+
+from soc.fu.test.common import TestCase
+from soc.fu.ldst.pipe_data import LDSTPipeSpec
+import random
+
+
+def get_cu_inputs(dec2, sim):
+    """naming (res) must conform to LDSTFunctionUnit input regspec
+    """
+    res = {}
+
+    # RA
+    reg1_ok = yield dec2.e.read_reg1.ok
+    if reg1_ok:
+        data1 = yield dec2.e.read_reg1.data
+        res['ra'] = sim.gpr(data1).value
+
+    # RB (or immediate)
+    reg2_ok = yield dec2.e.read_reg2.ok
+    if reg2_ok:
+        data2 = yield dec2.e.read_reg2.data
+        res['rb'] = sim.gpr(data2).value
+
+    # RC
+    reg3_ok = yield dec2.e.read_reg3.ok
+    if reg3_ok:
+        data3 = yield dec2.e.read_reg3.data
+        res['rc'] = sim.gpr(data3).value
+
+    # XER.so
+    oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+    if oe:
+        so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+        res['xer_so'] = so
+
+    return res
+
+
+class LDSTTestCase(FHDLTestCase):
+    test_data = []
+
+    def __init__(self, name):
+        super().__init__(name)
+        self.test_name = name
+
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
+        self.test_data.append(tc)
+
+    def test_load_store(self):
+        lst = ["stw 2, 0(1)",
+               "lwz 3, 0(1)"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0010
+        initial_regs[2] = 0x1234
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_ilang(self):
+        pspec = LDSTPipeSpec(id_wid=2)
+        alu = LDSTBasePipe(pspec)
+        vl = rtlil.convert(alu, ports=alu.ports())
+        with open("ldst_pipeline.il", "w") as f:
+            f.write(vl)
+
+