(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 006f573e06b3270c570ed39b91e5c0114c527d73..6f1c1ea992e2838e6e1f4dd95264b7a74459520b 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -732,15 +732,15 @@ Where:
 
 Bit-allocation Summary:
 
-* EXT3nn and three other encodings provide space for non-Simple-V
-  operations to have QTY 4of EXTn00-EXTn47 Primary Opcode ranges
+* EXT3nn and other areas provide space for up to
+  QTY 4of non-Vectoriseable EXTn00-EXTn47 ranges.
 * QTY 3of 55-bit spaces also exist for future use (longer by 3 bits
   than opcodes allocated in EXT001)
 * Simple-V EXT2nn is restricted to range EXT248-263
 * non-Simple-V EXT2nn (if ever allocated by a future RFC) is restricted to range EXT200-247
 * Simple-V EXT0nn takes up 50% of PO9 for this and future Simple-V RFCs
-* The clear separation between Simple-V and non-Simple-V means there is
-  no possibility of future RFCs encroaching on the others' space.
+* The clear separation between Simple-V and non-Simple-V stops
+  conflict in future RFCs.
 
 \newpage{}
 
@@ -751,7 +751,7 @@ Power ISA v3.1 Section 1.6.3 Book I calls it a "defined word".
 
 | 0-5    | 6-31   |
 |--------|--------|
-| PO     | EXT000-063 Scalar (v3.0 or v3.1) operation |
+| PO     | EXT000-063 "Defined word" |
 
 **SVP64Single:{EXT000-063}** bit6=old  bit7=scalar
 
@@ -770,7 +770,7 @@ Augmenting EXT001 or EXT009 is prohibited.
 
 **SVP64:{EXT000-063}** bit6=old bit7=vector
 
-This encoding is identical to **SVP64:{EXT200-263}** except it
+This encoding is identical to **SVP64:{EXT248-263}** except it
 is the Vectorisation of existing v3.0/3.1 Scalar-words, EXT000-063.
 All the same rules apply with the addition that
 Vectorisation of EXT001 or EXT009 is prohibited.