connect XICS core irq to Decode2 eint

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 90a1bf0c1d879049d322dac662743d3c9069e4f0..cba01c7b70e9662aef6d23cbd5e6337b90fa6bf6 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -66,11 +66,6 @@ def sort_fuspecs(fuspecs):
 class NonProductionCore(Elaboratable):
     def __init__(self, pspec):
 
-        # add external interrupt?
-        self.xics = hasattr(pspec, "xics") and pspec.xics == True
-        if self.xics:
-            self.ext_irq_i = Signal()
-
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
         pi = self.l0.l0.dports[0]

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 17ca9df6ac61c42537c9f8183118f0114dc60913..788fdcacf5da57a18e3bdae4f2ec04905924ccde 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -107,12 +107,15 @@ class TestIssuer(Elaboratable):
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
 
+        # current state (MSR/PC at the moment
+        cur_state = CoreState("cur")
+
         # XICS interrupt handler
         if self.xics:
             m.submodules.xics_icp = icp = self.xics_icp
             m.submodules.xics_ics = ics = self.xics_ics
             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
-            comb += core.ext_irq_i.eq(icp.core_irq_o) # connect ICP to core
+            comb += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 
         # GPIO test peripheral
         if self.gpio:
@@ -148,9 +151,6 @@ class TestIssuer(Elaboratable):
         comb += self.busy_o.eq(core.busy_o)
         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 
-        # current state (MSR/PC at the moment
-        cur_state = CoreState("cur")
-
         # temporary hack: says "go" immediately for both address gen and ST
         l0 = core.l0
         ldst = core.fus.fus['ldst0']