[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Sat, 4 Apr 2020 11:10:08 +0000 (11:10 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 4 Apr 2020 11:10:09 +0000 (12:10 +0100)
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+Date: Sat, 04 Apr 2020 11:10:08 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: whitequark@whitequark.org
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-276-13-f7SJvEHnP5@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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