more backporting work

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 8a3ad3a7d35f51c9695acf82e52d325bd611d580..01dc9e567e40ea0b8c755b4046e96c80d4f3d1e2 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -11,6 +11,7 @@ entity toplevel is
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
        SIM_MAIN_BRAM     : boolean  := false;
+       SIM_BRAM_CHAINBOOT  : positive  := 0;
        EXTERNAL_CORE     : boolean  := false;
        CLK_INPUT     : positive := 100000000;
        CLK_FREQUENCY : positive := 100000000;
@@ -89,6 +90,7 @@ begin
     soc0: entity work.soc
        generic map(
            MEMORY_SIZE   => MEMORY_SIZE,
+           SIM_BRAM_CHAINBOOT  => SIM_BRAM_CHAINBOOT,
            SIM_MAIN_BRAM   => SIM_MAIN_BRAM,
            RAM_INIT_FILE => RAM_INIT_FILE,
            SIM           => false,

diff --git a/soc.vhdl b/soc.vhdl
index 65f535fd53f89b17c190455c4a3ccaf4dcbdddc8..f46b3533613a58bf7f90a58958c2416e721a97ae 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -68,7 +68,7 @@ entity soc is
         ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
        HAS_DRAM           : boolean  := false;
        SIM_MAIN_BRAM      : boolean  := false;
-       --FIXME: SIM_BRAM_CHAINBOOT      : positive  := 0;
+       SIM_BRAM_CHAINBOOT : positive  := 0;
        DRAM_SIZE          : integer := 0;
        RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
     -- hack to jump-start alternative (e.g. verilator-loaded linux kernel)
@@ -869,6 +869,7 @@ begin
            BRAM_SIZE => MEMORY_SIZE,
            DRAM_SIZE => DRAM_SIZE,
            DRAM_INIT_SIZE => DRAM_INIT_SIZE,
+           SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT,
            CLK_FREQ => CLK_FREQ,
            HAS_SPI_FLASH => HAS_SPI_FLASH,
            SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,

diff --git a/syscon.vhdl b/syscon.vhdl
index 97a42770728fcc903774f9d5f94ea3e7c5801da4..e8cbf1db28e34d49de042fa03ec93281601fb5b6 100644 (file)
--- a/syscon.vhdl
+++ b/syscon.vhdl
@@ -12,6 +12,7 @@ entity syscon is
        CLK_FREQ         : integer;
        HAS_UART         : boolean;
        HAS_DRAM         : boolean;
+       SIM_BRAM_CHAINBOOT : integer;
        BRAM_SIZE        : integer;
        DRAM_SIZE        : integer;
        DRAM_INIT_SIZE   : integer;
@@ -54,6 +55,7 @@ architecture behaviour of syscon is
     constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111";
     constant SYS_REG_UART0_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000";
     constant SYS_REG_UART1_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001";
+    constant SYS_REG_BRAM_BOOTADDR : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001010";
 
     -- Muxed reg read signal
     signal reg_out     : std_ulogic_vector(63 downto 0);
@@ -118,6 +120,7 @@ architecture behaviour of syscon is
     signal info_fl_off   : std_ulogic_vector(31 downto 0);
     signal uinfo_16550   : std_ulogic;
     signal uinfo_freq    : std_ulogic_vector(31 downto 0);
+    signal reg_brambootaddr  : std_ulogic_vector(63 downto 0);
 
     -- Wishbone response latch
     signal wb_rsp        : wb_io_slave_out;
@@ -149,6 +152,7 @@ begin
                  SYS_REG_INFO_HAS_URTU   => info_has_urtu,
                 others => '0');
 
+    reg_brambootaddr <= std_ulogic_vector(to_unsigned(SIM_BRAM_CHAINBOOT, 64));
     reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
     reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
                    else (others => '0');
@@ -187,6 +191,7 @@ begin
        reg_spiinfo     when SYS_REG_SPIFLASHINFO,
         reg_uart0info   when SYS_REG_UART0_INFO,
         reg_uart1info   when SYS_REG_UART1_INFO,
+        reg_brambootaddr when SYS_REG_BRAM_BOOTADDR,
        (others => '0') when others;
     wb_rsp.dat   <= reg_out(63 downto 32) when wishbone_in.adr(0) = '1' else
                   reg_out(31 downto 0);