reformat declarations to look like test file, bit hacky...

diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py
index 0226ab6b438a168e091b88ba96f80a82f7e87b4a..985dfa047842d6769468281fc2f05b61c016dc8f 100644 (file)
--- a/src/bsv/interface_decl.py
+++ b/src/bsv/interface_decl.py
@@ -21,13 +21,15 @@ class Pin(object):
                  enabled=True,
                  io=False,
                  action=False,
-                 bitspec=None):
+                 bitspec=None,
+                 outenmode=False):
         self.name = name
         self.ready = ready
         self.enabled = enabled
         self.io = io
         self.action = action
         self.bitspec = bitspec if bitspec else 'Bit#(1)'
+        self.outenmode = outenmode
 
     def ifacefmt(self, fmtfn):
         res = '    '
@@ -195,6 +197,10 @@ class Interface(object):
     def ifacefmtdecfn2(self, name):
         return name
 
+    def ifacefmtdecfn3(self, name):
+        """ HACK! """
+        return "%s_outenX" % name
+
     def ifacefmtoutfn(self, name):
         return "wr%s" % name
 
@@ -209,8 +215,14 @@ class Interface(object):
         return pin.ifacefmt(self.ifacefmtdecfn)
 
     def ifacefmtpin(self, pin):
-        return pin.ifacedef(self.ifacefmtoutfn, self.ifacefmtinfn,
-                            self.ifacefmtdecfn2)
+        decfn = self.ifacefmtdecfn2
+        outfn = self.ifacefmtoutfn
+        print pin, pin.outenmode
+        if pin.outenmode:
+            decfn = self.ifacefmtdecfn3
+            outfn = self.ifacefmtoutenfn
+        return pin.ifacedef(outfn, self.ifacefmtinfn,
+                            decfn)
 
     def ifacedef(self, *args):
         res = '\n'.join(map(self.ifacefmtpin, self.pins))
@@ -226,6 +238,9 @@ class MuxInterface(Interface):
 
 class IOInterface(Interface):
 
+    def ifacefmtoutenfn(self, name):
+        return "cell{0}_mux_outen"
+
     def ifacefmtoutfn(self, name):
         """ for now strip off io{0}_ part """
         return "cell{0}_mux_out"
@@ -336,7 +351,8 @@ mux_interface = MuxInterface('cell', [{'name': 'mux', 'ready': False,
 
 io_interface = IOInterface(
     'io',
-    [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
+    [{'name': 'cell_out', 'enabled': False, },
+     {'name': 'cell_outen', 'enabled': False, 'outenmode': True, },
      {'name': 'inputval', 'action': True, 'io': True}, ])
 
 # == Peripheral Interface definitions == #

diff --git a/src/bsv/wire_def.py b/src/bsv/wire_def.py
index 59431a2a41a816d5b433b27f21f3c04fb1c7787b..3838709f8d58442c781a6a28cbaa50bb45cb45c3 100644 (file)
--- a/src/bsv/wire_def.py
+++ b/src/bsv/wire_def.py
@@ -2,6 +2,7 @@
 muxwire = '''
       Wire#({1}) wrcell{0}_mux<-mkDWire(0);'''
 generic_io = '''
-      GenericIOType cell{0}_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell{0}_mux_out<-mkDWire(0);
+      Wire#(Bit#(1)) cell{0}_mux_outen<-mkDWire(0);
       Wire#(Bit#(1)) cell{0}_mux_in<-mkDWire(0);
 '''