update ternlogi to be identical to xxeval (ls007), to make it clear

that this is supposed to be exactly like xxeval.
even refer to the same table

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index e6f215c7584fdd8172bab7fe29eee4719984e710..f828eb800b685301537b83d4384ce09d83f82b31 100644 (file)
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -177,26 +177,30 @@ Add this section to Book I 3.3.13
 Pseudocode:
 
 ```
-src1 <- VSR[32xAX+A]
-src2 <- VSR[32xBX+B]
-src3 <- VSR[32xCX+C]
-result <- (~src1&~src2&~src3 & qword_bit_splat(IMM.bit[0]) |
-         (~src1&~src2& src3 & qword_bit_splat(IMM.bit[1]) |
-         (~src1& src2&~src3 & qword_bit_splat(IMM.bit[2]) |
-         (~src1& src2& src3 & qword_bit_splat(IMM.bit[3]) |
-         ( src1&~src2&~src3 & qword_bit_splat(IMM.bit[4]) |
-         ( src1&~src2& src3 & qword_bit_splat(IMM.bit[5]) |
-         ( src1& src2&~src3 & qword_bit_splat(IMM.bit[6]) |
-         ( src1& src2& src3 & qword_bit_splat(IMM.bit[7])
-VSR[32xTX+T] â\86\90 result
-
-result <- [0] * 64
-do i = 0 to 63
-    idx <- (RT)[i] || (RA)[i] || (RB)[i]  # compute index from current bits
-    result[i] <- TLI[7 - idx]  # subtract from 7 to index in LSB0 order
+RT <- VSR[32xAX+A]
+RA <- VSR[32xBX+B]
+RB <- VSR[32xCX+C]
+result <- (~RT&~RA&~RB & TLI[0]*XLEN |
+          (~RT&~RA& RB & TLI[1]*XLEN |
+          (~RT& RA&~RB & TLI[2]*XLEN |
+          (~RT& RA& RB & TLI[3]*XLEN |
+          ( RT&~RA&~RB & TLI[4]*XLEN |
+          ( RT&~RA& RB & TLI[5]*XLEN |
+          ( RT& RA&~RB & TLI[6]*XLEN |
+          ( RT& RA& RB & TLI[7]*XLEN)
 RT <- result
 ```
 
+For each integer value i, 0 to XLEN-1, do the following.
+
+    Let j be the value of the concatenation of the
+    contents of bit i of RT, bit i of RB, bit i of RT.
+    The value of bit j of TLI is placed into bit i of RT.
+
+    See Table 145, "xxeval(A, B, C, TLI) Equivalent
+    Functions," on page 968 for the equivalent function
+    evaluated by this instruction for any given value of TLI.
+
 Special registers altered:
 
 ```