files.append({f : {'file_type' : 'verilogSource'}})
f = os.path.join(gen_dir, "litedram-wrapper.vhdl")
files.append({f : {'file_type' : 'vhdlSource-2008'}})
+ f = os.path.join(gen_dir, "litedram-initmem.vhdl")
+ files.append({f : {'file_type' : 'vhdlSource-2008'}})
f = os.path.join(gen_dir, "litedram_core.init")
files.append({f : {'file_type' : 'user'}})
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+ port (
+ clk : in std_ulogic;
+ wb_in : in wb_io_master_out;
+ wb_out : out wb_io_slave_out
+ );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+ constant INIT_RAM_SIZE : integer := 16384;
+ constant INIT_RAM_ABITS :integer := 14;
+ constant INIT_RAM_FILE : string := "litedram_core.init";
+
+ type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+ impure function init_load_ram(name : string) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ variable ram_line : line;
+ begin
+ for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ hread(ram_line, temp_word);
+ temp_ram(i*2) := temp_word(31 downto 0);
+ temp_ram(i*2+1) := temp_word(63 downto 32);
+ end loop;
+ return temp_ram;
+ end function;
+
+ signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+ attribute ram_style : string;
+ attribute ram_style of init_ram: signal is "block";
+
+begin
+
+ init_ram_0: process(clk)
+ variable adr : integer;
+ begin
+ if rising_edge(clk) then
+ wb_out.ack <= '0';
+ if (wb_in.cyc and wb_in.stb) = '1' then
+ adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+ if wb_in.we = '0' then
+ wb_out.dat <= init_ram(adr);
+ else
+ for i in 0 to 3 loop
+ if wb_in.sel(i) = '1' then
+ init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+ wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+ end if;
+ end loop;
+ end if;
+ wb_out.ack <= '1';
+ end if;
+ end if;
+ end process;
+
+ wb_out.stall <= '0';
+
+end architecture rtl;
if mw_init:
src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
src_init_file = build_init_code(build_dir)
+ src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
else:
write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl")
src_init_file = os.path.join(gw_dir, "mem.init")
+ src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl")
# Copy generated files to target dir, amend them if necessary
core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, "litedram_core.init")
dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl")
+ dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
replace_in_file(core_file, "mem.init", "litedram_core.init")
shutil.copy(core_file, t_dir)
shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_wrap_file, dst_wrap_file)
+ shutil.copyfile(src_initram_file, dst_initram_file)
def main():
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+ port (
+ clk : in std_ulogic;
+ wb_in : in wb_io_master_out;
+ wb_out : out wb_io_slave_out
+ );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+ wb_out.dat <= (others => '0');
+ wb_out.stall <= '0';
+ wb_out.ack <= wb_in.stb and wb_in.cyc;
+
+end architecture rtl;
library work;
use work.wishbone_types.all;
-use work.sim_console.all;
entity litedram_wrapper is
generic (
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
- constant INIT_RAM_SIZE : integer := 16384;
- constant INIT_RAM_ABITS :integer := 14;
- constant INIT_RAM_FILE : string := "litedram_core.init";
-
- type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
-
- impure function init_load_ram(name : string) return ram_t is
- file ram_file : text open read_mode is name;
- variable temp_word : std_logic_vector(63 downto 0);
- variable temp_ram : ram_t := (others => (others => '0'));
- variable ram_line : line;
- begin
- for i in 0 to (INIT_RAM_SIZE/8)-1 loop
- exit when endfile(ram_file);
- readline(ram_file, ram_line);
- hread(ram_line, temp_word);
- temp_ram(i*2) := temp_word(31 downto 0);
- temp_ram(i*2+1) := temp_word(63 downto 32);
- end loop;
- return temp_ram;
- end function;
-
- signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
-
- attribute ram_style : string;
- attribute ram_style of init_ram: signal is "block";
-
begin
-- alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
- -- BRAM Memory slave. TODO: Pipeline it with an output buffer
- -- to improve timing
- init_ram_0: process(system_clk)
- variable adr : integer;
- begin
- if rising_edge(system_clk) then
- wb_init_out.ack <= '0';
- if (wb_init_in.cyc and wb_init_in.stb) = '1' then
- adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 2))));
- if wb_init_in.we = '0' then
- wb_init_out.dat <= init_ram(adr);
- else
- for i in 0 to 3 loop
- if wb_init_in.sel(i) = '1' then
- init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
- wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
- end if;
- end loop;
- end if;
- wb_init_out.ack <= '1';
- end if;
- end if;
- end process;
+ -- Init code BRAM memory slave
+ init_ram_0: entity work.dram_init_mem
+ port map(
+ clk => system_clk,
+ wb_in => wb_init_in,
+ wb_out => wb_init_out
+ );
--
-- Control bus wishbone: This muxes the wishbone to the CSRs
library work;
use work.wishbone_types.all;
-use work.sim_console.all;
entity litedram_wrapper is
generic (
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+ port (
+ clk : in std_ulogic;
+ wb_in : in wb_io_master_out;
+ wb_out : out wb_io_slave_out
+ );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+ constant INIT_RAM_SIZE : integer := 16384;
+ constant INIT_RAM_ABITS :integer := 14;
+ constant INIT_RAM_FILE : string := "litedram_core.init";
+
+ type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+ impure function init_load_ram(name : string) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ variable ram_line : line;
+ begin
+ for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ hread(ram_line, temp_word);
+ temp_ram(i*2) := temp_word(31 downto 0);
+ temp_ram(i*2+1) := temp_word(63 downto 32);
+ end loop;
+ return temp_ram;
+ end function;
+
+ signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+ attribute ram_style : string;
+ attribute ram_style of init_ram: signal is "block";
+
+begin
+
+ init_ram_0: process(clk)
+ variable adr : integer;
+ begin
+ if rising_edge(clk) then
+ wb_out.ack <= '0';
+ if (wb_in.cyc and wb_in.stb) = '1' then
+ adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+ if wb_in.we = '0' then
+ wb_out.dat <= init_ram(adr);
+ else
+ for i in 0 to 3 loop
+ if wb_in.sel(i) = '1' then
+ init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+ wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+ end if;
+ end loop;
+ end if;
+ wb_out.ack <= '1';
+ end if;
+ end if;
+ end process;
+
+ wb_out.stall <= '0';
+
+end architecture rtl;
library work;
use work.wishbone_types.all;
-use work.sim_console.all;
entity litedram_wrapper is
generic (
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
- constant INIT_RAM_SIZE : integer := 16384;
- constant INIT_RAM_ABITS :integer := 14;
- constant INIT_RAM_FILE : string := "litedram_core.init";
-
- type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
-
- impure function init_load_ram(name : string) return ram_t is
- file ram_file : text open read_mode is name;
- variable temp_word : std_logic_vector(63 downto 0);
- variable temp_ram : ram_t := (others => (others => '0'));
- variable ram_line : line;
- begin
- for i in 0 to (INIT_RAM_SIZE/8)-1 loop
- exit when endfile(ram_file);
- readline(ram_file, ram_line);
- hread(ram_line, temp_word);
- temp_ram(i*2) := temp_word(31 downto 0);
- temp_ram(i*2+1) := temp_word(63 downto 32);
- end loop;
- return temp_ram;
- end function;
-
- signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
-
- attribute ram_style : string;
- attribute ram_style of init_ram: signal is "block";
-
begin
-- alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
- -- BRAM Memory slave. TODO: Pipeline it with an output buffer
- -- to improve timing
- init_ram_0: process(system_clk)
- variable adr : integer;
- begin
- if rising_edge(system_clk) then
- wb_init_out.ack <= '0';
- if (wb_init_in.cyc and wb_init_in.stb) = '1' then
- adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 2))));
- if wb_init_in.we = '0' then
- wb_init_out.dat <= init_ram(adr);
- else
- for i in 0 to 3 loop
- if wb_init_in.sel(i) = '1' then
- init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
- wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
- end if;
- end loop;
- end if;
- wb_init_out.ack <= '1';
- end if;
- end if;
- end process;
+ -- Init code BRAM memory slave
+ init_ram_0: entity work.dram_init_mem
+ port map(
+ clk => system_clk,
+ wb_in => wb_init_in,
+ wb_out => wb_init_out
+ );
--
-- Control bus wishbone: This muxes the wishbone to the CSRs
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-16 19:06:01
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:27
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_bankmachine0_row_close = 1'd0;
reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
wire litedramcore_bankmachine1_req_valid;
wire litedramcore_bankmachine1_req_ready;
reg litedramcore_bankmachine1_row_close = 1'd0;
reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
wire litedramcore_bankmachine2_req_valid;
wire litedramcore_bankmachine2_req_ready;
reg litedramcore_bankmachine2_row_close = 1'd0;
reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
wire litedramcore_bankmachine3_req_valid;
wire litedramcore_bankmachine3_req_ready;
reg litedramcore_bankmachine3_row_close = 1'd0;
reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
wire litedramcore_bankmachine4_req_valid;
wire litedramcore_bankmachine4_req_ready;
reg litedramcore_bankmachine4_row_close = 1'd0;
reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
wire litedramcore_bankmachine5_req_valid;
wire litedramcore_bankmachine5_req_ready;
reg litedramcore_bankmachine5_row_close = 1'd0;
reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
wire litedramcore_bankmachine6_req_valid;
wire litedramcore_bankmachine6_req_ready;
reg litedramcore_bankmachine6_row_close = 1'd0;
reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
wire litedramcore_bankmachine7_req_valid;
wire litedramcore_bankmachine7_req_ready;
reg litedramcore_bankmachine7_row_close = 1'd0;
reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
wire litedramcore_ras_allowed;
wire litedramcore_cas_allowed;
reg litedramcore_steerer6 = 1'd1;
reg litedramcore_steerer7 = 1'd1;
wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
reg litedramcore_trrdcon_count = 1'd0;
wire litedramcore_tfawcon_valid;
(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
wire [2:0] litedramcore_tfawcon_count;
reg [4:0] litedramcore_tfawcon_window = 5'd0;
wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
reg litedramcore_tccdcon_count = 1'd0;
wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
reg [2:0] litedramcore_twtrcon_count = 3'd0;
wire litedramcore_read_available;
wire litedramcore_write_available;
litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine0_row <= 14'd0;
litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
litedramcore_bankmachine0_trascon_count <= 3'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine1_row <= 14'd0;
litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
litedramcore_bankmachine1_trascon_count <= 3'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine2_row <= 14'd0;
litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
litedramcore_bankmachine2_trascon_count <= 3'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine3_row <= 14'd0;
litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
litedramcore_bankmachine3_trascon_count <= 3'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine4_row <= 14'd0;
litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
litedramcore_bankmachine4_trascon_count <= 3'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine5_row <= 14'd0;
litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
litedramcore_bankmachine5_trascon_count <= 3'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine6_row <= 14'd0;
litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
litedramcore_bankmachine6_trascon_count <= 3'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine7_row <= 14'd0;
litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
litedramcore_bankmachine7_trascon_count <= 3'd0;
litedramcore_choose_cmd_grant <= 3'd0;
litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd1;
+ litedramcore_trrdcon_ready <= 1'd0;
litedramcore_trrdcon_count <= 1'd0;
litedramcore_tfawcon_ready <= 1'd1;
litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd1;
+ litedramcore_tccdcon_ready <= 1'd0;
litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd1;
+ litedramcore_twtrcon_ready <= 1'd0;
litedramcore_twtrcon_count <= 3'd0;
litedramcore_time0 <= 5'd0;
litedramcore_time1 <= 4'd0;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+ port (
+ clk : in std_ulogic;
+ wb_in : in wb_io_master_out;
+ wb_out : out wb_io_slave_out
+ );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+ constant INIT_RAM_SIZE : integer := 16384;
+ constant INIT_RAM_ABITS :integer := 14;
+ constant INIT_RAM_FILE : string := "litedram_core.init";
+
+ type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+ impure function init_load_ram(name : string) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ variable ram_line : line;
+ begin
+ for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ hread(ram_line, temp_word);
+ temp_ram(i*2) := temp_word(31 downto 0);
+ temp_ram(i*2+1) := temp_word(63 downto 32);
+ end loop;
+ return temp_ram;
+ end function;
+
+ signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+ attribute ram_style : string;
+ attribute ram_style of init_ram: signal is "block";
+
+begin
+
+ init_ram_0: process(clk)
+ variable adr : integer;
+ begin
+ if rising_edge(clk) then
+ wb_out.ack <= '0';
+ if (wb_in.cyc and wb_in.stb) = '1' then
+ adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+ if wb_in.we = '0' then
+ wb_out.dat <= init_ram(adr);
+ else
+ for i in 0 to 3 loop
+ if wb_in.sel(i) = '1' then
+ init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+ wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+ end if;
+ end loop;
+ end if;
+ wb_out.ack <= '1';
+ end if;
+ end if;
+ end process;
+
+ wb_out.stall <= '0';
+
+end architecture rtl;
library work;
use work.wishbone_types.all;
-use work.sim_console.all;
entity litedram_wrapper is
generic (
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
- constant INIT_RAM_SIZE : integer := 16384;
- constant INIT_RAM_ABITS :integer := 14;
- constant INIT_RAM_FILE : string := "litedram_core.init";
-
- type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
-
- impure function init_load_ram(name : string) return ram_t is
- file ram_file : text open read_mode is name;
- variable temp_word : std_logic_vector(63 downto 0);
- variable temp_ram : ram_t := (others => (others => '0'));
- variable ram_line : line;
- begin
- for i in 0 to (INIT_RAM_SIZE/8)-1 loop
- exit when endfile(ram_file);
- readline(ram_file, ram_line);
- hread(ram_line, temp_word);
- temp_ram(i*2) := temp_word(31 downto 0);
- temp_ram(i*2+1) := temp_word(63 downto 32);
- end loop;
- return temp_ram;
- end function;
-
- signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
-
- attribute ram_style : string;
- attribute ram_style of init_ram: signal is "block";
-
begin
-- alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
- -- BRAM Memory slave. TODO: Pipeline it with an output buffer
- -- to improve timing
- init_ram_0: process(system_clk)
- variable adr : integer;
- begin
- if rising_edge(system_clk) then
- wb_init_out.ack <= '0';
- if (wb_init_in.cyc and wb_init_in.stb) = '1' then
- adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 2))));
- if wb_init_in.we = '0' then
- wb_init_out.dat <= init_ram(adr);
- else
- for i in 0 to 3 loop
- if wb_init_in.sel(i) = '1' then
- init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
- wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
- end if;
- end loop;
- end if;
- wb_init_out.ack <= '1';
- end if;
- end if;
- end process;
+ -- Init code BRAM memory slave
+ init_ram_0: entity work.dram_init_mem
+ port map(
+ clk => system_clk,
+ wb_in => wb_init_in,
+ wb_out => wb_init_out
+ );
--
-- Control bus wishbone: This muxes the wishbone to the CSRs
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-16 19:06:03
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:29
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_bankmachine0_row_close = 1'd0;
reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
wire litedramcore_bankmachine1_req_valid;
wire litedramcore_bankmachine1_req_ready;
reg litedramcore_bankmachine1_row_close = 1'd0;
reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
wire litedramcore_bankmachine2_req_valid;
wire litedramcore_bankmachine2_req_ready;
reg litedramcore_bankmachine2_row_close = 1'd0;
reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
wire litedramcore_bankmachine3_req_valid;
wire litedramcore_bankmachine3_req_ready;
reg litedramcore_bankmachine3_row_close = 1'd0;
reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
wire litedramcore_bankmachine4_req_valid;
wire litedramcore_bankmachine4_req_ready;
reg litedramcore_bankmachine4_row_close = 1'd0;
reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
wire litedramcore_bankmachine5_req_valid;
wire litedramcore_bankmachine5_req_ready;
reg litedramcore_bankmachine5_row_close = 1'd0;
reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
wire litedramcore_bankmachine6_req_valid;
wire litedramcore_bankmachine6_req_ready;
reg litedramcore_bankmachine6_row_close = 1'd0;
reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
wire litedramcore_bankmachine7_req_valid;
wire litedramcore_bankmachine7_req_ready;
reg litedramcore_bankmachine7_row_close = 1'd0;
reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
wire litedramcore_ras_allowed;
wire litedramcore_cas_allowed;
reg litedramcore_steerer6 = 1'd1;
reg litedramcore_steerer7 = 1'd1;
wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
reg litedramcore_trrdcon_count = 1'd0;
wire litedramcore_tfawcon_valid;
(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
wire [2:0] litedramcore_tfawcon_count;
reg [4:0] litedramcore_tfawcon_window = 5'd0;
wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
reg litedramcore_tccdcon_count = 1'd0;
wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1;
+(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
reg [2:0] litedramcore_twtrcon_count = 3'd0;
wire litedramcore_read_available;
wire litedramcore_write_available;
litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine0_row <= 15'd0;
litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
litedramcore_bankmachine0_trascon_count <= 3'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine1_row <= 15'd0;
litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
litedramcore_bankmachine1_trascon_count <= 3'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine2_row <= 15'd0;
litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
litedramcore_bankmachine2_trascon_count <= 3'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine3_row <= 15'd0;
litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
litedramcore_bankmachine3_trascon_count <= 3'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine4_row <= 15'd0;
litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
litedramcore_bankmachine4_trascon_count <= 3'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine5_row <= 15'd0;
litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
litedramcore_bankmachine5_trascon_count <= 3'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine6_row <= 15'd0;
litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
litedramcore_bankmachine6_trascon_count <= 3'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
litedramcore_bankmachine7_row <= 15'd0;
litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
litedramcore_bankmachine7_trascon_count <= 3'd0;
litedramcore_choose_cmd_grant <= 3'd0;
litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd1;
+ litedramcore_trrdcon_ready <= 1'd0;
litedramcore_trrdcon_count <= 1'd0;
litedramcore_tfawcon_ready <= 1'd1;
litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd1;
+ litedramcore_tccdcon_ready <= 1'd0;
litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd1;
+ litedramcore_twtrcon_ready <= 1'd0;
litedramcore_twtrcon_count <= 3'd0;
litedramcore_time0 <= 5'd0;
litedramcore_time1 <= 4'd0;
projects / microwatt.git / commitdiff