make SR Latch async again, make busy signal sync into issue unit

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 5cc54540e7a76930c119a8807d55f913baa4cbfb..e3f19c661c4cb0364e635cf4f1e3744c03d3c418 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -140,12 +140,12 @@ class Scoreboard(Elaboratable):
         for i, fu in enumerate(il):
             fn_issue_l.append(fu.issue_i)
             fn_busy_l.append(fu.busy_o)
-            # XXX sync, so as to stop a simulation infinite loop
             m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
             m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
             m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
             m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
-            m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
+            # XXX sync, so as to stop a simulation infinite loop
+            m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
 
         #---------
         # connect Function Units

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index ba4e192911af19a8f056f4e1a40a82081928e45f..a21911d300fa9e665a14de93a0141e970579332b 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -79,7 +79,7 @@ class FnUnit(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.submodules.rd_l = rd_l = SRLatch(sync=False)
-        m.submodules.wr_l = wr_l = SRLatch(sync=True)
+        m.submodules.wr_l = wr_l = SRLatch(sync=False)
         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
         m.submodules.src1_d = src1_d = Decoder(self.reg_width)
         m.submodules.src2_d = src2_d = Decoder(self.reg_width)