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diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ba9caca0b2a80856c7dae79afaa747b793a5ec5f..e846822857f88dae289ca6ac54e4d6224c0aae11 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -615,7 +615,7 @@ class TestIssuerInternal(Elaboratable):
         sv_changed = Signal() # note write to SVSTATE
 
         # read state either from incoming override or from regfile
-        # TODO: really should be doing MSR in the same say
+        # TODO: really should be doing MSR in the same way
         pc = state_get(m, self.pc_i, "pc",                  # read PC
                             self.state_r_pc, StateRegs.PC)
         svstate = state_get(m, self.svstate_i, "svstate",   # read SVSTATE