[submodule "litex/soc/software/compiler_rt"]
path = litex/soc/software/compiler_rt
url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+ path = litex/soc/cores/cpu/picorv32/verilog
+ url = https://github.com/cliffordwolf/picorv32
graft litex/soc/software
graft litex/soc/cores/cpu/lm32/verilog
graft litex/soc/cores/cpu/mor1kx/verilog
+graft litex/soc/cores/cpu/picorv32/verilog
\ No newline at end of file
--- /dev/null
+from litex.soc.cores.cpu.picorv32.core import PicoRV32
--- /dev/null
+import os
+
+from litex.gen import *
+
+from litex.soc.interconnect import wishbone
+
+
+class PicoRV32(Module):
+ def __init__(self, platform, progaddr_reset):
+ self.ibus = i = wishbone.Interface()
+ self.dbus = d = wishbone.Interface()
+ self.interrupt = Signal(32)
+
+ # # #
+
+ mem_valid = Signal()
+ mem_instr = Signal()
+ mem_ready = Signal()
+ mem_addr = Signal(32)
+ mem_wdata = Signal(32)
+ mem_wstrb = Signal(4)
+ mem_rdata = Signal(32)
+
+ self.specials += Instance("picorv32",
+ p_ENABLE_COUNTERS=1,
+ p_ENABLE_REGS_16_31=1,
+ p_ENABLE_REGS_DUALPORT=1,
+ p_LATCHED_MEM_RDATA=0,
+ p_TWO_STAGE_SHIFT=1,
+ p_TWO_CYCLE_COMPARE=0,
+ p_TWO_CYCLE_ALU=0,
+ p_CATCH_MISALIGN=1,
+ p_CATCH_ILLINSN=1,
+ p_ENABLE_PCPI=0,
+ p_ENABLE_MUL=0,
+ p_ENABLE_IRQ=0,
+ p_ENABLE_IRQ_QREGS=1,
+ p_ENABLE_IRQ_TIMER=1,
+ p_MASKED_IRQ=0x00000000,
+ p_LATCHED_IRQ=0xffffffff,
+ p_PROGADDR_RESET=progaddr_reset,
+ p_PROGADDR_IRQ=0x00000010,
+
+ i_clk=ClockSignal(),
+ i_resetn=~ResetSignal(),
+
+ o_mem_valid=mem_valid,
+ o_mem_instr=mem_instr,
+ i_mem_ready=mem_ready,
+
+ o_mem_addr=mem_addr,
+ o_mem_wdata=mem_wdata,
+ o_mem_wstrb=mem_wstrb,
+ i_mem_rdata=mem_rdata,
+
+ o_mem_la_read=Signal(), # Not used
+ o_mem_la_write=Signal(), # Not used
+ o_mem_la_addr=Signal(32), # Not used
+ o_mem_la_wdata=Signal(32), # Not used
+ o_mem_la_wstrb=Signal(4), # Not used
+
+ o_pcpi_valid=Signal(), # Not used
+ o_pcpi_insn=Signal(32), # Not used
+ o_pcpi_rs1=Signal(32), # Not used
+ o_pcpi_rs2=Signal(32), # Not used
+ i_pcpi_wr=0,
+ i_pcpi_rd=0,
+ i_pcpi_wait=0,
+ i_pcpi_ready=0,
+
+ i_irq=self.interrupt,
+ o_eoi=Signal(32) # Not used
+ )
+
+ self.comb += [
+ i.adr.eq(mem_addr[2:]),
+ i.dat_w.eq(mem_wdata),
+ i.we.eq(mem_wstrb != 0),
+ i.sel.eq(mem_wstrb),
+ i.cyc.eq(mem_valid & mem_instr),
+ i.stb.eq(mem_valid & mem_instr),
+ i.cti.eq(0),
+ i.bte.eq(0),
+ If(mem_instr,
+ mem_ready.eq(i.ack),
+ mem_rdata.eq(i.dat_r),
+ ),
+
+ d.adr.eq(mem_addr[2:]),
+ d.dat_w.eq(mem_wdata),
+ d.we.eq(mem_wstrb != 0),
+ d.sel.eq(mem_wstrb),
+ d.cyc.eq(mem_valid & ~mem_instr),
+ d.stb.eq(mem_valid & ~mem_instr),
+ d.cti.eq(0),
+ d.bte.eq(0),
+ If(~mem_instr,
+ mem_ready.eq(d.ack),
+ mem_rdata.eq(d.dat_r)
+ )
+ ]
+
+ # add Verilog sources
+ vdir = os.path.join(
+ os.path.abspath(os.path.dirname(__file__)), "verilog")
+ platform.add_source(os.path.join(vdir, "picorv32.v"))
--- /dev/null
+Subproject commit e630bedda4f16d5f061f93879177a2d6b2a66d29
from litex.soc.interconnect.csr import CSRStatus
+cpu_endianness = {
+ "lm32": "big",
+ "or1k": "big",
+ "riscv32": "little"
+}
def get_cpu_mak(cpu):
if cpu == "lm32":
triple = "or1k-linux"
cpuflags = "-mhard-mul -mhard-div -mror -mffl1 -maddc"
clang = "1"
+ elif cpu == "riscv32":
+ triple = "riscv32-unknown-elf"
+ cpuflags = "-mno-save-restore"
+ clang = ""
else:
raise ValueError("Unsupported CPU type: "+cpu)
return [
("TRIPLE", triple),
("CPU", cpu),
("CPUFLAGS", cpuflags),
+ ("CPUENDIANNESS", cpu_endianness[cpu]),
("CLANG", clang)
]
def get_linker_output_format(cpu_type):
- return "OUTPUT_FORMAT(\"elf32-{}\")\n".format(cpu_type)
+ linker_output_formats = {
+ "lm32": "elf32-lm32",
+ "or1k": "elf32-or1k",
+ "riscv32": "elf32-littleriscv"
+ }
+ return "OUTPUT_FORMAT(\"" + linker_output_formats[cpu_type] + "\")\n"
def get_linker_regions(regions):
from litex.gen import *
from litex.soc.cores import identifier, timer, uart
-from litex.soc.cores.cpu import lm32, mor1kx
+from litex.soc.cores.cpu import lm32, mor1kx, picorv32
from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(mor1kx.MOR1KX(platform, self.cpu_reset_address))
+ elif cpu_type == "riscv32":
+ self.add_cpu_or_bridge(picorv32.PicoRV32(platform, self.cpu_reset_address))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
def soc_core_args(parser):
parser.add_argument("--cpu-type", default=None,
- help="select CPU: lm32, or1k")
+ help="select CPU: lm32, or1k, riscv32")
parser.add_argument("--integrated-rom-size", default=None, type=int,
help="size/enable the integrated (BIOS) ROM")
parser.add_argument("--integrated-main-ram-size", default=None, type=int,
--- /dev/null
+.section .text, "ax", @progbits
+.global boot_helper
+boot_helper:
+ nop
__asm__ volatile("nop");
#elif defined (__or1k__)
__asm__ volatile("l.nop");
+#elif defined (__riscv__)
+ __asm__ volatile("nop");
#else
#error Unsupported architecture
#endif
return ie;
#elif defined (__or1k__)
return !!(mfspr(SPR_SR) & SPR_SR_IEE);
+#elif defined (__riscv__)
+ /* FIXME */
+ return 0;
#else
#error Unsupported architecture
#endif
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
else
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
+#elif defined (__riscv__)
+ /* FIXME */
+ return 0;
#else
#error Unsupported architecture
#endif
return mask;
#elif defined (__or1k__)
return mfspr(SPR_PICMR);
+#elif defined (__riscv__)
+ /* FIXME */
+ return 0;
#else
#error Unsupported architecture
#endif
__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
#elif defined (__or1k__)
mtspr(SPR_PICMR, mask);
+#elif defined (__riscv__)
+ /* FIXME */
+ return 0;
#else
#error Unsupported architecture
#endif
return pending;
#elif defined (__or1k__)
return mfspr(SPR_PICSR);
+#elif defined (__riscv__)
+ /* FIXME */
+ return 0;
#else
#error Unsupported architecture
#endif
--- /dev/null
+.global _start
+_start:
+ /* zero-initialize all registers */
+ addi x1, zero, 0
+ addi x2, zero, 0
+ addi x3, zero, 0
+ addi x4, zero, 0
+ addi x5, zero, 0
+ addi x6, zero, 0
+ addi x7, zero, 0
+ addi x8, zero, 0
+ addi x9, zero, 0
+ addi x10, zero, 0
+ addi x11, zero, 0
+ addi x12, zero, 0
+ addi x13, zero, 0
+ addi x14, zero, 0
+ addi x15, zero, 0
+ addi x16, zero, 0
+ addi x17, zero, 0
+ addi x18, zero, 0
+ addi x19, zero, 0
+ addi x20, zero, 0
+ addi x21, zero, 0
+ addi x22, zero, 0
+ addi x23, zero, 0
+ addi x24, zero, 0
+ addi x25, zero, 0
+ addi x26, zero, 0
+ addi x27, zero, 0
+ addi x28, zero, 0
+ addi x29, zero, 0
+ addi x30, zero, 0
+ addi x31, zero, 0
+
+ /* jump to main */
+ jal ra, main
for (i = 0; i < cache_size; i += cache_block_size)
mtspr(SPR_ICBIR, i);
+#elif defined (__riscv__)
+ /* no instruction cache */
+ asm volatile("nop");
#else
#error Unsupported architecture
#endif
for (i = 0; i < cache_size; i += cache_block_size)
mtspr(SPR_DCBIR, i);
+#elif defined (__riscv__)
+ /* no data cache */
+ asm volatile("nop");
#else
#error Unsupported architecture
#endif
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
#elif defined (__or1k__)
__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
+#elif defined (__riscv__)
+ /* FIXME */
+ asm volatile("nop");
#else
#error Unsupported architecture
#endif
include ../include/generated/variables.mak
include $(SOC_DIRECTORY)/software/common.mak
+ifeq ($(CPU),big)
CFLAGS+=-D_YUGA_LITTLE_ENDIAN=0 -D_YUGA_BIG_ENDIAN=1 -Wno-missing-prototypes
+else
+CFLAGS+=-D_YUGA_LITTLE_ENDIAN=1 -D_YUGA_BIG_ENDIAN=0 -Wno-missing-prototypes
+endif
-OBJECTS=divsi3.o modsi3.o comparesf2.o comparedf2.o negsf2.o negdf2.o addsf3.o subsf3.o mulsf3.o divsf3.o lshrdi3.o muldi3.o divdi3.o ashldi3.o ashrdi3.o udivmoddi4.o \
+OBJECTS=umodsi3.o udivsi3.o mulsi3.o divsi3.o modsi3.o comparesf2.o comparedf2.o negsf2.o negdf2.o addsf3.o subsf3.o mulsf3.o divsf3.o lshrdi3.o muldi3.o divdi3.o ashldi3.o ashrdi3.o udivmoddi4.o \
floatsisf.o floatunsisf.o fixsfsi.o fixdfdi.o fixunssfsi.o fixunsdfdi.o adddf3.o subdf3.o muldf3.o divdf3.o floatsidf.o floatunsidf.o floatdidf.o fixdfsi.o fixunsdfsi.o \
clzsi2.o ctzsi2.o udivdi3.o umoddi3.o moddi3.o ucmpdi2.o
--- /dev/null
+
+long
+__mulsi3(unsigned long a, unsigned long b)
+{
+long res = 0;
+while (a)
+{
+if (a & 1)
+{
+res += b;
+}
+b <<= 1;
+a >>=1;
+}
+return res;
+}
\ No newline at end of file
projects / litex.git / commitdiff