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diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index dca3bed2074c3a5de3bf924e26a79b5eb814a370..319ff875c866d28a3eb1f701cb764bc27ef652a3 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -286,17 +286,19 @@ an instruction Defined Word space must have the exact same Instruction
 and exact same Instruction Encoding in all spaces (including
 being RESERVED if UnVectoriseable) or not be allocated at all.
 This is required as an inviolate hard rule governing Primary Opcode 9
-that may not be revoked under any circumstances*
+that may not be revoked under any circumstances. A useful way to think
+of this is that the Prefix Encoding is, like the 8086 REP instruction,
+an independent 32-bit Defined Word.*
 
 # Remapped Encoding (`RM[0:23]`)
 
 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits 32-37 are
 the Primary Opcode of the Suffix "Defined Word". 38-63 are the remainder of the
 Defined Word.  Note that the new EXT232-263 SVP64 area it is obviously mandatory
-that bit 32 is required to be set.
+that bit 32 is required to be set to 1.
 
 | 0-5 | 6 | 7 | 8-31     | 32-37  | 38-64    |Description                        |
-|-----|---|---|----------|--------|----------|----------------------------------|
+|-----|---|---|----------|--------|----------|-----------------------|
 | PO  | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263     |
 | PO  | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063       |