corrections to sof and sif out of mask mode

diff --git a/openpower/sv/sbf.py b/openpower/sv/sbf.py
index 1885a3929c8fc2d0aaf886c1b73866f84e1ab0b2..c2eee4c882759f842c054fe53177b0bbc879cf9f 100644 (file)
--- a/openpower/sv/sbf.py
+++ b/openpower/sv/sbf.py
@@ -1,5 +1,5 @@
-def sbf(RA, mask=None):
-    RT = RA if mask is not None else 0
+def sbf(RA, mask=None, zero=False):
+    RT = RA if mask is not None and not zero else 0
     i = 0
     # start setting if no predicate or if 1st predicate bit set
     setting_mode = mask is None
@@ -7,6 +7,8 @@ def sbf(RA, mask=None):
         bit = 1<<i
         if not setting_mode and mask is not None and (mask & bit):
             setting_mode = True # back into "setting" mode
+        if setting_mode and mask is not None and not (mask & bit):
+            setting_mode = False # disable when no mask bit
         if setting_mode:
             if RA & bit: # found a bit in rs1: stop setting RT
                 setting_mode = False
@@ -19,7 +21,7 @@ if __name__ == '__main__':
      m  = 0b11000011
      v3 = 0b10010100 # vmsbf.m v2, v3
      v2 = 0b01000011 # v2
-     RT = sbf(v3, m)
+     RT = sbf(v3, m, zero=True)
      print(bin(v3), bin(v2), bin(RT))
      v3 = 0b10010100 # vmsbf.m v2, v3
      v2 = 0b00000011 # v2 contents

diff --git a/openpower/sv/sif.py b/openpower/sv/sif.py
index 9f2455f2ec7f79ebb69fbac15491d208c9c001f2..1f68cc1222688789dfa567b9251c52e5b03b2727 100644 (file)
--- a/openpower/sv/sif.py
+++ b/openpower/sv/sif.py
@@ -1,5 +1,5 @@
-def sif(RA, mask=None):
-    RT = RA if mask is not None else 0
+def sif(RA, mask=None, zero=False):
+    RT = RA if mask is not None and not zero else 0
     i = 0
     # start setting if no predicate or if 1st predicate bit set
     setting_mode = mask is None
@@ -7,6 +7,8 @@ def sif(RA, mask=None):
         bit = 1<<i
         if not setting_mode and mask is not None and (mask & bit):
             setting_mode = True # back into "setting" mode
+        if setting_mode and mask is not None and not (mask & bit):
+            setting_mode = True # masked out, stop setting
         if setting_mode:
             if RA & bit: # found a bit in rs1: stop setting RT
                 setting_mode = False
@@ -18,7 +20,7 @@ if __name__ == '__main__':
      m  = 0b11000011
      v3 = 0b10010100 # vmsif.m v2, v3
      v2 = 0b11000011 # v2
-     RT = sif(v3, m)
+     RT = sif(v3, m, zero=True)
      print(bin(v3), bin(v2), bin(RT))
      v3 = 0b10010100 # vmsif.m v2, v3
      v2 = 0b00000111 # v2 contents