add walkthrough video for memory and cache

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index da2caaf3e91145a9950408499645e78e5aa0ae0a..19695e3d9661baa82b843ffd5b50599a3e14b3a9 100644 (file)
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -6,6 +6,8 @@ expected to run at one-to-one from an external 24 mhz to 100 mhz clock.
 The requirements are therefore **radically different** from the next
 roadmap ASIC.
 
+Walkthrough video: <https://youtu.be/6Yiyw4abJpE>
+
 Basic diagram:
 
 [[!img 180nm_single_core_testasic_memlayout.jpg size="600x"]]