(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 011a3e9fbb5fd53e43c1eb6404067c117ede5d1c..1ea5c8a91802997ed77053661ceb6eb3c54bad06 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -77,6 +77,8 @@ An autogenerator containing CSV files is available so that the task of creating
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
 
+Note when decoding the RM intobits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
+
 Links:
 
 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>