(no commit message)

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index d4051aad1ff27aa21d4e4b7db5dd8a4a54e07bbe..7d6f0388843a79120995c4593612e61c3d753cae 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -434,7 +434,7 @@ The only one missing from the list here, because it is non-sequential,
 is VGATHER: moving registers by specifying a vector of register indices
 (`regs[rd] = regs[regs[rs]]` in a loop).  This one is tricky because it
 typically does not exist in standard scalar ISAs.  If it did it would
-be called [[sv/mv.x]]
+be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER.
 
 # CR predicate result analysis