(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 87464645bc0ef29b23f79568be25b33c95bcd5d1..ae41ea98c5b759fd0236109c14267b6e6a8a61bc 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -236,11 +236,11 @@ there are additional setb conditional instructions in v3.1 (p129)
 
     RT = (CR[BI] == 1) ? 1 : 0
 
-which also negate that, and also return -1 / 0.  these are similar yo crweird but not the same purpose.  most notable is that crweird acts on CR fields rather than the entire 32 bit CR.
+which also negate that, and also return -1 / 0.  these are similar to crweird but not the same purpose.  most notable is that crweird acts on CR fields rather than the entire 32 bit CR.
 
 # Predication Examples
 
-let us take the following example:
+Take the following example:
 
     r10 = 0b00010
     sv.mtcrweird/dm=r10/dz cr8.v, 0, 0b0011.0000